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LTM4602IV#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LTM4602
19
4602fa
Figure 21. Typical Application, 5V to 20V Input, 0.6V to 5V Output, 6A Max
Figure 20. V
IN
to V
OUT
Step-Down Ratio for 12V
IN
to 5V
OUT
and 5V
IN
to 3.3V
OUT
5V to 3.3V at 5A
12V to 5V at 5A
4602 F20a
R
SET
22.1k
1%
R1
30.1k
EXTV
CC
RUN/SS
COMP
FCB
V
OUT
5V TO 3.3V AT 5A WITH f
ADJ
= 30.1k C1, C3: TDK C3216X5R1E106MT
C2: TAIYO YUDEN, JMK316BJ226ML
C4: SANYO POSCAP, 6TPE330MIL
PGOOD
V
OSET
SV
IN
PGNDSGND
V
IN
4.5V TO 7V
V
OUT
3.3V AT 5A
C1
10μF
25V
C3
10μF
25V
C4
330μF
6.3V
C2
22μF
C5
100pF
V
IN
LTM4602
f
ADJ
RUN/SOFT-START
OPEN DRAIN
EFFICIENCY = 94%
AT 5A LOAD
+
4602 F20b
R
SET
13.7k
1%
R1
15k
EXTV
CC
RUN/SS
COMP
FCB
V
OUT
7V TO 20V AT 5A WITH f
ADJ
= 15k C1, C3: TDK C3216X5R1E106MT
C2: TAIYO YUDEN, JMK316BJ226ML
C4: SANYO POSCAP, 6TPE330MIL
PGOOD
V
OSET
SV
IN
PGNDSGND
V
IN
7V TO 20V
V
OUT
5V AT 5A
EFFICIENCY = 92.5%
AT 5A LOAD
C1
10μF
25V
C3
10μF
25V
C4
330μF
6.3V
C2
22μF
C5
100pF
V
IN
LTM4602
f
ADJ
RUN/SOFT-START
OPEN DRAIN
+
4602 F21
V
OUT
EXTV
CC
f
ADJ
V
OSET
FCB
COMP
PGOOD
V
OUT
(MULTIPLE PINS)
V
OUT
6A
RUN/SS
SGND
PGND
(MULTIPLE PINS)
C
OUT1
REFER TO
TABLE 2
C
OUT2
REFER TO
TABLE 2
GND
0.6V TO 5V
REFER TO STEP-DOWN
RATIO GRAPH
C4
OPT
V
IN
5V TO 20V
GND
C
IN
10μF
×2
CER
C
IN
150μF
BULK
C3
100pF
R
SET
66.5k
REFER TO
TABLE 1
V
IN
(MULTIPLE PINS)
LTM4602
SV
IN
+
+
APPLICATIONS INFORMATION
LTM4602
20
4602fa
4602 TA02
R
SET
15.8k
1%
EXTV
CC
RUN
COMP
FCB
V
OUT
V
OUT
= 0.6V • ([100k/N] + R
SET
)/R
SET
WHERE N = 2
C1, C7: TDK C3216X5R1E106MT
C2, C9: TAIYO YUDEN, JMK316BJ226ML-T501
C5, C10: SANYO POSCAP, 4TPE330MI
PGOOD
V
OSET
SV
IN
PGNDSGND
V
OUT
2.5V
12A
V
IN
4.5V TO 20V
C7
10μF
25V
C1
10μF
25V
C10
330μF
4V
C9
22μF
V
IN
LTM4602
f
ADJ
R1
100k
EXTV
CC
RUN
COMP
FCB
V
OUT
PGOOD
V
OSET
SV
IN
PGNDSGND
RUN/SOFT-START
C4
220pF
C5
330μF
4V
C2
22μF
V
IN
LTM4602
f
ADJ
+
+
Current Sharing Between Two
LTM4602 Modules
Parallel Operation and Load Sharing
TOTAL LOAD
0
INDIVIDUAL SHARE
6
4
2
0
6
4602 TA03
12
I
OUT1
I
OUT2
12V
IN
2.5V
OUT
12A
MAX
TYPICAL APPLICATION
LTM4602
21
4602fa
LGA Package
104-Lead (15mm × 15mm)
(Reference LTM DWG # 05-05-1800)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
LAND DESIGNATION PER JESD MO-222, SPP-010
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. THE TOTAL NUMBER OF PADS: 104
4
3
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER IS A MARKED FEATURE OR A
NOTCHED BEVELED PAD
SYMBOL
aaa
bbb
eee
TOLERANCE
0.15
0.10
0.15
2.72 – 2.92
DETAIL B
DETAIL B
SUBSTRATE
MOLD
CAP
0.27 – 0.37
2.45 – 2.55
bbb Z
Z
15
BSC
TOP VIEW
15
BSC
4
PAD 1
CORNER
X
Y
aaa Z
aaa Z
13.97
BSC
12.70
BSC
0.11 – 0.27
13.93
BSC
35
24
79
68
11 13
10 12
15 17
14 16
19 21
18 20 22
LGA104 0206
BOTTOM VIEW
C(0.30)
PAD 1
3
PADS
SEE NOTES
94
95 96 97 98
99 100 101 102 103
104
93
82
71
60
49
24
23
22
21
20
1918171676543
2
40
51
62
73
84 85 86 87 88 89 90 91
74 75 76 77 78 79 80
63 64 65 66 67 68 69
52 53 54 55 56 57 58
42 43 44 45 46 47
92
81
70
59
48
11109
13 14 15
26 27 28 29 30 31
33 34 35 36 37 38
41
1
8
12
25
32
39
50
61
72
83
M
YXeee
1
SUGGESTED SOLDER PAD LAYOUT
TOP VIEW
94
95 96 97 98
99 100 101 102 103
104
93
82
71
60
49
24
23
22
21
20
19
1817
16
7
6
5
4
3
2
40
51
62
73
84 85 86 87
88
89 90 91
74 75 76
77
78 79 80
63
64
65
66
67
68 69
52
53
54
55
56
57
58
42 43
44
45
46
47
92
81
70
59
48
11
10
9
13 14 15
26
27
28 29 30 31
33 34
35
36
37
38
41
1
8
12
25
32
39
50
61
72
83
0.0000
1.2700
2.5400
0.3175
0.3175
4.4450
5.7150
6.9850
1.4675
5.7158
6.9421
4.4458
6.3500
6.3500
3.8100
3.8100
1.2700
0.3175
0.3175
0.0000
1.2700
3.1758
1.9058
0.6358
0.0000
0.6342
1.9042
3.1742
4.4442
5.7142
6.9865
2.7375
4.0075
5.2775
6.5475
6.9888
1.0900
2.3600
4.4950
5.7650
5.0800
5.0800
2.5400
2.5400
23
A
B
C
D
E
F
G
H
J
L
M
N
P
R
T
K
PACKAGE DESCRIPTION
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LTM4602IV#PBF

Mfr. #:
Buy LTM4602IV#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 20V, 6A Step-down Module Regulator
Lifecycle:
New from this manufacturer.
Delivery:
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