Document #: 38-07450 Rev. *D Page 4 of 7
Figure 2. Test and Measurement Setup
Voltage and Timing Definitions
f
ΔXO
V
CXO
pullability range Nominal pullability for -3,-5 ±150 – – ppm
f
ΔXO
V
CXO
pullability range Extended pullability for -4 – ±200 – ppm
V
VCXO
V
CXO
input range 0 – V
DD
V
R
UP
Pull up resistor on inputs V
DD
= 3.14 to 3.47V, measured at V
IN
= 0V – 100 150 kΩ
DC Electrical Specifications (continued)
Parameter
[1]
Name Description Min Typ. Max Unit
AC Electrical Specifications
Parameter
[1]
Name Description Min Typ. Max Unit
DC Output Duty Cycle Duty Cycle is defined in Figure 3; t1/t2, 50% of
V
DD
45 50 55 %
ER
1
Rising Edge Rate for -3,-4 Output Clock Edge Rate, Measured from 20% to
80% of V
DD
, C
LOAD
= 15 pF See Figure 4.
0.8 1.4 – V/ns
EF
1
Falling Edge Rate for -3,-4 Output Clock Edge Rate, Measured from 80% to
20% of V
DD
, C
LOAD
= 15 pF See Figure 4.
0.8 1.4 – V/ns
ER
2
Rising Edge Rate for -5 Output Clock Edge Rate, Measured from 20% to
80% of V
DD
, C
LOAD
= 15 pF See Figure 4.
1.0 1.8 – V/ns
EF
2
Falling Edge Rate for -5 Output Clock Edge Rate, Measured from 80% to
20% of V
DD
, C
LOAD
= 15 pF See Figure 4.
1.0 1.8 – V/ns
t
9
Clock Jitter CLK1, CLK2 Peak-Peak period jitter – 120 – ps
t
10
PLL Lock Time – – 3 ms
0.1
μ
F
V
DDs
Outputs
C
LOAD
GND
DUT
Clock
Output
V
DD
50% of V
DD
0V
t
1
t
2
Figure 3. Duty Cycle Definition
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