74SSTV16859NLG8

4
INDUSTRIAL TEMPERATURE RANGE
IDT74SSTV16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
OPERATING CHARACTERISTICS, TA = 25ºC
(1)
Symbol Parameter Min. Typ.
(1)
Max. Unit
VDD Supply Voltage VDDQ 2.7 V
VDDQ Output Supply Voltage 2.3 2.5 2.7 V
VREF Reference Voltage (VREF= VDDQ/2) 1.15 1.25 1.35 V
VTT Termination Voltage VREF– 40mV VREF VREF+ 40mV V
VI Input Voltage 0 VDD V
VIH AC High-Level Input Voltage Data Inputs VREF+ 310mV V
VIL AC Low-Level Input Voltage Data Inputs VREF– 310mV V
VIH DC High-Level Input Voltage Data Inputs VREF+ 150mV V
VIL DC Low-Level Input Voltage Data Inputs VREF– 150mV V
VIH High-Level Input Voltage RESET 1.7 V
VIL Low-Level Input Voltage RESET 0.7 V
VICR Common-Mode Input Range CLK, CLK 0.97 1.53 V
VI (PP) Peak-to-Peak Input Voltage CLK, CLK 360 mV
IOH High-Level Output Current 20 mA
IOL Low-Level Output Current 20
TA Operating Free-Air Temperature 40 +85 °C
NOTE:
1. The RESET input of the device must be held at VDD or GND to ensure proper device operation.
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
VDD = 2.5V ± 0.2V
Symbol Parameter Min Max. Unit
fMAX 200 M Hz
tPD CLK and CLK to Q 1.1 2.8 ns
tPHL RESET to Q 5 ns
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
VDD = 2.5V ± 0.2V
Symbol Parameter Min. Max. Unit
CLOCK Clock Frequency 200 MHz
tw Pulse Duration, CLK, CLK HIGH or LOW 2.5 ns
tACT Differential Inputs Active Time
(1)
—22ns
tINACT Differential Inputs Inactive Time
(2)
—22ns
tSU Setup Time, Fast Slew Rate
(3, 5)
Data Before CLK, CLK 0.75 ns
Setup Time, Slow Slew Rate
(4, 5)
0.9 ns
tN Hold Time, Fast Slew Rate
(3,5)
Data Before CLK, CLK 0.75 ns
Hold Time, Slow Slew Rate
(2,5)
0.9 ns
NOTES:
1. Data inputs must be low a minimum time of tACT max., after RESET is taken HIGH.
2. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max., after RESET is taken LOW.
3. For data signal input slew rate is 1V/ns.
4. For data signal input slew rate is 0.5V/ns and <1V/ns.
5. CLK, CLK signal input slew rates are 1V/ns.
5
INDUSTRIAL TEMPERATURE RANGE
IDT74SSTV16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
TEST CIRCUITS AND WAVEFORMS (VDD = 2.5V ± 0.2V)
Voltage Waveforms - Pulse Duration
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.
3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPLH and tPHL are the same as tPD.
Load Circuit
Voltage Waveforms - Setup and Hold Times
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Propagation Delay Times
Voltage and Current Waveforms
Inputs Active and Inactive Times
Timing
Input
V
ICR
VI(PP)
tPLH tPHL
Output
VOH
VOL
VICR
VTT VTT
VOH
VOL
VIH
VIL
tPHL
VDD/2
V
TT
LVCMO S
RESET
Input
Output
VREF
VIH
VIL
VREF
Input
tW
VREF
VIH
VIL
VREF
Input
VICR VI(PP)
tSU tN
Timing
Input
From Output
Under Test
V
TT
RL =50Ω
C
L =30pF
(see note 1)
Test Point
LVCMOS
RESET
Input
V
DD/2
V
DD
tINACT tACT
IDD
VDD/2
90%
0V
(see note 2)
10%
6
INDUSTRIAL TEMPERATURE RANGE
IDT74SSTV16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
ORDERING INFORMATION
CORPORATE HEADQUARTERS for SALES:
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
XX XX X XX
Packa geDevice TypeTemp. Range
PA
NL
Thin Shrink Small Outline Package
Thermally Enhanced Plastic Very Fine Pitch
Quad Flat No Lead Package
74
13-Bit to 26-Bit Re gistered Buffer with SSTL I/O
–40°C to +85°C
SST V
859
16
XX
Family
Double-Density

74SSTV16859NLG8

Mfr. #:
Manufacturer:
IDT
Description:
Registers 13TO26BIT REG BUFFER SSTL
Lifecycle:
New from this manufacturer.
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