9 2004 Semtech Corp. www.semtech.com
SC2738
POWER MANAGEMENT
F119
107.33
1014
C
3
6
)MIN(BULK
µ=
•
••
=
−
−
So if we use 1% V
OUT
set resistors we would select 2 x
>100µF, 18mΩ POSCAPs for output capacitance (which
assumes that local ceramic bypass capacitors will
absorb the balance of the (9 - 8.4)mΩ ESR
requirement - otherwise 15mΩ capacitors should be
used).
If we use 0.1% set resistors, then the total DC error
becomes ±3.85% = ±57.8mV, leaving ±3.15% = 47.2mV
for the ESR spike. In this case:
Ω== m8.11
A4
mV2.47
R
)MAX(ESR
and
F85
102.47
1014
C
3
6
)MIN(BULK
µ=
•
••
=
−
−
So for 0.1% resistors we could use 1 x 100µF, 12mΩ
POSCAPs for output capacitance.
The input capacitance needs to be large enough to stop
the input supply from collapsing below -5% (i.e. the
design minimum) during output load steps. If the input to
the pass MOSFET is not local to the supply bulk
capacitance then additional bulk capacitance may be
required.
MOSFET selection: since the input voltage to the SC2738
is 5V±5%, the minimum available gate drive is:
V825.2)575.14.4(V
GS
=−=
So a MOSFET rated for V
GS
= 2.7V will be required, with
an R
DS(ON)(MAX)
(over temp.) given by:
Ω=
−
=
−
= m22
4
)5.1375.2(
I
)VV(
R
)MAX(OUT
OUT)MIN(IN
)MAX)ON(DS
Obviously, if a 12V rail is available to power the SC2738,
the number of FET options increases dramatically.
Layout Guidelines
The advantages of using the SC2738 to drive external
MOSFETs are a) that the bandgap reference and control
circuitry are in a die that does not contain high power
dissipating devices and b) that the device itself does not
need to be located right next to the power devices. Thus
very accurate output voltages can be obtained since
changes due to heating effects will be minimal.
The 0.1µF bypass capacitor should be located close to
the supply (IN) and GND pins, and connected directly to
the ground plane.
The feedback resistors should be located at the device,
with the sense line from the output routed from the load
(or top end of the droop resistor if passive droop is being
used) directly to the feedback chain. If passive droop is
being used, the droop resistor should be located right at
the load to avoid adding additional unplanned droop.
Sense and drive lines should be routed away from noisy
traces or components.
For very low input to output voltage differentials, the
input to output / load path should be as wide and short
as possible. Where greater headroom is available, wide
traces may suffice.
Power dissipation within the device is practically
negligible, thus requiring no special consideration during
layout. The MOSFET pass devices should be laid out
according to the manufacturer’s guidelines for the power
being dissipated within them.
Applications Infomation (Cont.)
