ISL24211IRTZ-T13

ISL24211
7
FN7585.0
February 23, 2011
The maximum value of I
DVR_OUT
can be calculated by
substituting the maximum register value of 255 into Equation 2,
resulting in Equation 3:
Equation 2 can also be used to calculate the unit sink current
step size per Register Code, resulting in Equation 4:
Determination of R
SET
The ultimate goal for the ISL24211 is to generate an adjustable
voltage between two endpoints, V
COM_MIN
and V
COM_MAX
, with
a fixed power supply voltage, AV
DD
. This is accomplished by
choosing the correct values for R
SET
, R
1
and R
2
. The exact value
of R
SET
is not critical. Values from 1k to more than 100k will
work under most conditions. The following expression calculates
the minimum R
SET
value:
Note that this is the absolute minimum value for R
SET
. Larger
R
SET
values reduce quiescent power, since R
1
and R
2
are
proportional to R
SET
. The ISL24211 is tested with a 5kΩ R
SET
.
Determination of R
1
and R
2
With AV
DD
, V
COM(MIN)
and V
COM(MAX)
known and R
SET
chosen
per the above requirements, R
1
and R
2
can be determined using
Equations 6 and 7:
Final Transfer Function
The voltage at DVR_OUT can be calculated from Equation 8:
With amplifier A2 in the unity-gain configuration (V
COM_OUT
tied
to IN
N
as shown in Figure 5), V
DVROUT
=V
COM_OUT
=V
COM
.
Example
As an example, suppose the A
VDD
supply is 15V, the desired
V
COM_MIN
= 6.5V and the desired V
COM_MAX
= 8.5V. R
SET
is
arbitrarily chosen to be 7.5kΩ.
First, verify that our chosen R
SET
meets the minimum
requirement described in Equation 5:
Using Equations 6 and 7, calculate the values of R
1
and R
2
:
Table 1 shows the resulting V
COM
voltage as a function of register
value for these conditions.
Output Voltage Span Calculation
It is also possible to calculate V
COM(MIN)
and V
COM(MAX)
from the
existing resistor values.
V
COM_MIN
occurs when the greatest current, I
DVR(MAX),
is drawn
from the middle node of the R1/R2 divider. Substituting
RegisterValue = 255 into Equation 8 gives the following:
Similarly, RegisterValue = 0 for V
COM(MAX)
:
I
DVROUT
MAX()
A
VDD
20R
SET
--------------------
=
(EQ. 3)
I
STEP
AV
DD
256()20()R
SET
()
----------------------------------------------
=
(EQ. 4)
R
SET
MIN()
AV
DD
16
--------------
V
OUT MIN()
AV
DD
20
--------------
⎝⎠
⎛⎞
------------------------------------------------------
⎝⎠
⎜⎟
⎜⎟
⎜⎟
⎜⎟
⎛⎞
kΩ()=
(EQ. 5)
R
1
5120 R
SET
V
COM MAX()
V
COM MIN()
256 V
COM MAX()
V
COM MIN()
-------------------------------------------------------------------------------- -
⎝⎠
⎜⎟
⎛⎞
=
(EQ. 6)
R
2
5120 R
SET
V
COM MAX()
V
COM MIN()
255 AV
DD
V
COM MIN()
256 V
COM MAX()
+
---------------------------------------------------------------------------------------------------------------------
⎝⎠
⎜⎟
⎛⎞
=
(EQ. 7)
V
DVROUT
AV
DD
R
2
R
1
R
2
+
--------------------
⎝⎠
⎜⎟
⎛⎞
1
RegisterValue 1+
256
---------------------------------------------------
R
1
20R
SET
--------------------
⎝⎠
⎜⎟
⎛⎞
⎝⎠
⎜⎟
⎛⎞
=
(EQ. 8)
TABLE 1. EXAMPLE V
DVR_OUT
vs REGISTER VALUE
REGISTER VALUE V
DVR_OUT
(V)
08.49
20 8.34
40 8.18
60 8.02
80 7.87
100 7.71
120 7.55
127 7.50
140 7.40
160 7.24
180 7.09
200 6.93
220 6.77
240 6.62
255 6.50
7.5kΩ()R
SET
MIN()
15
16
------ -
6.5V
15
20
------ -
⎝⎠
⎛⎞
------------------------------
⎝⎠
⎜⎟
⎜⎟
⎜⎟
⎛⎞
0.163kΩ==
⎝⎠
⎜⎟
⎜⎟
⎜⎟
⎛⎞
>
(EQ. 9)
R
1
5120 7500
8.5 6.5
256 8.5 6.5
------------------------------------- -
⎝⎠
⎛⎞
⋅⋅ 35.4kΩ==
(EQ. 10)
R
2
5120 7500
8.5 6.5
255 15 6.5 256 8.5+
------------------------------------------------------------------
⎝⎠
⎛⎞
⋅⋅ 46.4kΩ==
(EQ. 11)
V
COM MIN()
AV
DD
R
2
R
1
R
2
+
--------------------
⎝⎠
⎜⎟
⎛⎞
1
R
1
20R
SET
--------------------
⎝⎠
⎜⎟
⎛⎞
⎝⎠
⎜⎟
⎛⎞
=
(EQ. 12)
V
COM MAX()
AV
DD
R
2
R
1
R
2
+
--------------------
⎝⎠
⎜⎟
⎛⎞
1
1
256
----------
R
1
20R
SET
--------------------
⎝⎠
⎜⎟
⎛⎞
⎝⎠
⎜⎟
⎛⎞
=
(EQ. 13)
ISL24211
8
FN7585.0
February 23, 2011
By finding the difference of Equation 13 and Equation 12, the total
span of V
COM
can be found:
Assuming that the I
DVROUT
(MIN) = 0 instead of I
STEP
, the
expression in Equation 14 simplifies to:
DVR_OUT Pin Leakage Current
When the voltage on the DVR_OUT pin is greater than 10V, an
additional leakage current flows into the pin in addition to the
I
SET
current. Figure 6 shows the I
SET
current and the DVR_OUT
pin current for DVR_OUT pin voltage up to 19V. In applications
where the voltage on the DVR_OUT pin will be greater than 10V,
the actual output voltage will be lower than the voltage
calculated by Equation 8. The graph in Figure 6 was measured
with R
SET
= 4.99kΩ.
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 7. When applying power, V
DD
should be applied before or
at the same time as AV
DD
. The minimum time for t
VS
is 0µs.
When removing power, the sequence of V
DD
and AV
DD
is not
important.
Do not remove V
DD
or AV
DD
within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
Operating and Programming
Supply Voltage and Current
To program the EEPROM, AV
DD
must be 10.8V. If programming
is not required, the ISL24211 will operate over an AV
DD
range of
4.5V to 19V.
During EEPROM programming, I
DD
and I
AVDD
will temporarily be
higher than their quiescent currents. Figure 8 shows a typical I
DD
and I
AVDD
current profile during EEPROM programming. The
current pulses are Erase and Write cycles. The EEPROM
programming algorithm is shown in Figure 9. The algorithm
attempts up to 4 erase cycles and 4 programming cycles,
however typical parts only require 1 cycle of each, sometimes 2
when AV
DD
is near the minimum 10.8V limit.
V
COM
SPAN AV
DD
R
2
R
1
R
2
+
--------------------
⎝⎠
⎜⎟
⎛⎞
1
1
256
----------
⎝⎠
⎛⎞
R
1
20R
SET
--------------------
⎝⎠
⎜⎟
⎛⎞
=
(EQ. 14)
V
COM
SPAN
R
1
R
2
R
1
R
2
+
--------------------
⎝⎠
⎜⎟
⎛⎞
AV
DD
20R
SET
--------------------
⎝⎠
⎜⎟
⎛⎞
R
1
R
2
R
1
R
2
+
--------------------
⎝⎠
⎜⎟
⎛⎞
I
DVROUT
MAX()==
(EQ. 15)
FIGURE 6. DVR_OUT PIN LEAKAGE CURRENT
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0 2 4 6 8 10 12 14 16 18 20
OUT PIN VOLTAGE (V)
CURRENT (mA)
OUT PIN CURRENT
SET PIN CURRENT
REGISTER = 255
V
DD
A
VDD
t
VS
FIGURE 7. POWER SUPPLY SEQUENCE
VDD
Programming
Current
~1ms
AVDD
Programming
Current
I
P
100ms
Max
2.7mA
200µA
50µA
90µA
25µA
FIGURE 8. I
DD
AND I
AVDD
CURRENT PROFILE DURING EEPROM
PROGRAMMING
ISL24211
9
FN7585.0
February 23, 2011
ISL24211 Programming
The ISL24211 accepts I
2
C bus address and data when the WP
pin is high. The ISL24211 ignores the I
2
C bus when the WP pin is
low. Figure 10 shows the serial data format for writing the
register and programming the EEPROM. Figure 11 shows the
serial data format for reading the DAC register. Table 2 shows the
truth table for reading and writing the device.
Programming the EEPROM memory transfers the current DAC
register value to the EEPROM and occurs when the control bits
select the programming mode and the AV
DD
voltage is >10.8V.
After the EEPROM programming cycle is started, the WP pin can
be returned to logic low while the EEPROM write completes,
which takes a maximum of 100ms.
The ISL24211 uses a 6-bit I
2
C address, which is “100111yx” for
the first transmitted byte. Bit x is the R/W bit, and Bit y is the LSB
(D0) of the DCP register code to be written. The complete read
and write protocol is shown in Figures 10 and 11.
I
2
C Bus Signals
The ISL24211 uses fixed voltages for its I
2
C thresholds, rather
than the percentage of V
DD
described in the I
2
C specification
(see Table 3). This should not cause a problem in most systems,
but the I
2
C logic levels in a specific design should be checked to
ensure they are compatible with the ISL24211.
FIGURE 9. EEPROM PROGRAMMING FLOWCHART
Erase Pulse
Start EEPROM
Programming
Are EEPROM
Cells Erased?
No
Yes
Write Pulse
Are
EEPROM Cells
Programmed?
EEPROM
Programming
Complete
No
Yes
TABLE 2. ISL24211 READ AND WRITE CONTROL
WP PIN R/W P FUNCTION
0 1 X Read Register.
0 0 1 Will acknowledge I
2
C
transactions. Will not write to
register.
0 0 0 Will acknowledge I
2
C
transactions. Will not write to
EEPROM.
1 1 X Read DAC Register.
101Write DAC Register.
100Program EEPROM.
TABLE 3. ISL24211 I
2
C BUS LOGIC LEVELS
SYMBOL ISL24211 I
2
C STANDARD
V
IL_I2C
0.55V 0.3*V
DD
V
IH_I2C
1.44V 0.7*V
DD

ISL24211IRTZ-T13

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
LCD Gamma Buffers ISL24211IRTZFREE VCO M DRVR + VCOM CLBTR
Lifecycle:
New from this manufacturer.
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