Publication Order Number:
NTF6P02T3/D
© Semiconductor Components Industries, LLC, 2013
August, 2013 − Rev. 6
1
NTF6P02, NVF6P02
Power MOSFET
-10 Amps, -20 Volts
P−Channel SOT−223
Features
• Low R
DS(on)
• Logic Level Gate Drive
• Diode Exhibits High Speed, Soft Recovery
• Avalanche Energy Specified
• NVF Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable*
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• Power Management in Portables and Battery−Powered Products,
i.e.: Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (T
J
= 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain−to−Source Voltage V
DSS
−20 Vdc
Gate−to−Source Voltage V
GS
±8.0 Vdc
Drain Current (Note 1)
− Continuous @ T
A
= 25°C
− Continuous @ T
A
= 70°C
− Single Pulse (t
p
= 10 ms)
I
D
I
D
I
DM
−10
−8.4
−35
Adc
Apk
Total Power Dissipation @ T
A
= 25°C P
D
8.3 W
Operating and Storage Temperature Range T
J
, T
stg
−55 to
+150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= −20 Vdc, V
GS
= −5.0 Vdc,
I
L(pk)
= −10 A, L = 3.0 mH, R
G
= 25W)
E
AS
150 mJ
Thermal Resistance
− Junction to Lead (Note 1)
− Junction to Ambient (Note 2)
− Junction to Ambient (Note 3)
R
q
JL
R
q
JA
R
q
JA
15
71.4
160
°C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
T
L
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Steady State.
2. When surface mounted to an FR4 board using 1” pad size,
(Cu. Area 1.127 sq in), Steady State.
3. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu. Area 0.412 sq in), Steady State.
1
2
3
4
−10 AMPERES
−20 VOLTS
R
DS(on)
= 44 mW (Typ.)
Device Package Shipping
†
ORDERING INFORMATION
SOT−223
CASE 318E
STYLE 3
MARKING DIAGRAM
& PIN ASSIGNMENT
http://onsemi.com
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
A = Assembly Location
Y = Year
W = Work Week
6P02 = Specific Device Code
G = Pb−Free Package
AYW
6P02G
G
1
Gate
2
Drain
3
Source
Drain
4
(Note: Microdot may be in either location)
SOT−223
(Pb−Free)
NTF6P02T3G
4000 / Tape &
Reel
G
S
D
P−Channel MOSFET
SOT−223
(Pb−Free)
NVF6P02T3G*
4000 / Tape &
Reel