LTC4010
16
4010fb
formed by C1 and the parallel combination of R1 and R2
is recommended for rejecting PWM switching noise. The
value of C1 should be chosen to yield a 1st order lowpass
frequency of less than 500Hz. In the case of a single cell,
the external application circuit shown in Figure 4 is rec-
ommended to provide the necessary noise filtering and
missing battery detection.
External Thermistor
The network for proper temperature sensing using a
thermistor with a negative temperature coefficient (NTC) is
shown in Figure 5. The LTC4010 is designed to work best
with a 1% 10k NTC thermistor with a b of 3750. However,
the LTC4010 will operate satisfactorily with other 10k NTC
thermistors having slightly different nominal exponential
temperature coefficients. For these thermistors, the tem-
perature related limits given in the Electrical Characteristics
table may not strictly apply. The filter formed by C1 in
Figure 5 is optional but recommended for rejecting PWM
switching noise.
applicaTions inForMaTion
on voltage inflection may not be adequate to protect the
battery from a severe overcharge.
INTV
DD
Regulator Output
If BGATE is left open, the INTV
DD
pin of the LTC4010 can be
used as an additional source of regulated voltage in the host
system any time READY is active. Switching loads on INTV
DD
may reduce the accuracy of internal analog circuits used to
monitor and terminate fast charging. In addition, DC current
drawn from the INTV
DD
pin can greatly increase internal
power dissipation at elevated V
CC
voltages. A minimum
ceramic bypass capacitor of 0.1µF is recommended.
Calculating Average Power Dissipation
The user should ensure that the maximum rated IC junction
temperature is not exceeded under all operating conditions.
The thermal resistance of the LTC4010 package (q
JA
)
is 38°C/W, provided the exposed metal pad is properly
soldered to the PCB. The actual thermal resistance in the
application will depend on the amount of PCB copper to
which the package is soldered. Feedthrough vias directly
below the package that connect to inner copper layers
are helpful in lowering thermal resistance. The following
formula may be used to estimate the maximum average
power dissipation P
D
(in watts) of the LTC4010 under
normal operating conditions.
P V mA I k Q Q
I
D CC DD TGATE BGATE
DD
= + + +
( )
9 615
3 85
( )
– .
++
+
60
30
2
n
V V
R
CC LED
LED
–
where:
I
DD
= Average external INTV
DD
load current, if any
Q
TGATE
= Gate charge of external P-channel MOSFET
in coulombs
Q
BGATE
= Gate charge of external N-channel MOSFET
(if used) in coulombs
V
LED
= Maximum external LED forward voltage
R
LED
= External LED current-limiting resistor used in
the application
n = Number of LEDs driven by the LTC4010
Figure 4. Single-Cell Monitor Network
10
7
BAT
10k
10k
33nF
1 CELL
4010 F04
V
CDIV
6
V
CELL
Figure 5. External NTC Thermistor Network
5
V
TEMP
R
T
10k NTC
C1
68nF
4010 F05
Disabling Thermistor Functions
Temperature sensing is optional in LTC4010 applications.
For low cost systems where temperature sensing may
not be required, the V
TEMP
pin may simply be wired to
GND through 10k to disable temperature qualification
of all charging operations. However, this practice is not
recommended for NiMH cells charged well above or below
their 1C rate, because fast charge termination based solely
