MAX132CWG Datasheet MAX132ENG+, MAX132EWG+T, MAX132CWG | P10-P12

MAX132

±18-Bit ADC with Serial Interface

10 ______________________________________________________________________________________

___________________Digital Interface

Serial data at DIN is sent in 8-bit packets and is shifted

into the internal 8-bit shift register with each rising edge

of SCLK. The data is then latched into either command

input register 0 or command input register 1, as deter-

mined by the LSB of the data sent, and is latched on

the rising edge of CHIP SELECT (CS) Data is clocked

out of the selected output register on each falling edge

of SCLK. D7(MSB) must be the first data bit to be shift-

ed in and is the first bit to be shifted out.

Output data is shifted out at the same time command

data is shifted in. Command data must be clocked in

on the previous 8-bit read-write cycle to receive con-

version data in the present cycle.

Since there is no internal power-on reset, initialize the

MAX132 immediately after power-up to insure correct

operation.

Table 2 defines each bit of five registers: the two com-

mand input registers, output register 0, output register

1, and the status output register.

Command Input Register 0

Data bits D1 and D2 of command register 0 (RS1 and

RS0) determine the data to be read on the data bus.

These bits select which register outputs data to the bus.

Table 3 defines the bit values that determine which reg-

ister is read on the next cycle (Figure 9).

Read-Zero Bit

The read-zero bit allows the ADC to calibrate on com-

mand for zero offset. The read-zero bit, when set to 1,

internally shorts the inputs; when a start-conversion

command is given, the zero error is converted. Subtract

the results from the standard external measurement

conversion when the read-zero conversion ends. If the

read-zero bit is set to 0, the converter measures the

voltage between IN Hl and IN LO once a start bit is

given. Take a new zero reading periodically and when-

ever the ambient temperature, the reference voltage, or

the common-mode input voltage are changed.

START, 

READ STATUS

CYCLE 1

INSTRUCTION

(DATA IN)

OUTPUT DATA

OUTPUT STATUS 

(EOC, POLARITY, B2–B0)

READ HIGHER

BITS

CYCLE 2

( B11–B18)

READ LOWER 

BITS

CYCLE 3

( B3–B10)

START, 

READ STATUS

CYCLE 4

Figure 9. Instruction and Data Sequencing

RS1

RS0

DEFINITIONS

Selects Register 0; output for data bits B3–B10

Selects Register 1; output for data bits B11–B18

Selects Register 2; output status for data bits

B0–B2, polarity, sleep, integrating, EOC, and

collision bit

1 1 Invalid data

Command Input

“1”

“0”

Start

Convert

Returns to

0 at EOC

Set P3

Output

Output Register 0

RS1 = 0, RS0 = 0

Output Register 1

RS1 = 0, RS0 = 1

“1”

50Hz

60Hz

Set P2

Output

B10

B18

MSB

Collision

B17

EOC

Sleep

Awake

Set P1

Output

B16

Integrating

Input

Table 3. Register Set-Bit Definitions

Table 2. Register Map of Input and Output Data

Read Zero

Read V

Set P0

Output

Don’t Care

RS0*

Don’t Care

B15

Sleep

B14

-Polarity

RS1*

Don’t Care

B13

B12

DATA BIT

B11

Output Status

RS1 = 1, RS0 = 0

“0” No Collision Converting

Not

Integrating

Awake +Polarity

B2 B1

LSB

*Note: Refer to Table 3.

D7 D6 D5 D4 D3 D2 D1 D0

MAX132

±18-Bit ADC with Serial Interface

______________________________________________________________________________________ 11

Averaging 2 or 3 read-zero measurements provides the

most accurate read-zero value. Perform a read-zero

sequence whenever a large change in the input voltage

is expected.

Sleep Bit

When the sleep bit is set to 1, (bit D5 in command input

returns high. In sleep mode, the supply current is typi-

cally 1µA and the oscillator shuts down. The interface

remains active and data can be read. When exiting

sleep mode, the analog circuitry needs time to stabilize

before the next conversion starts. Accomplish this by

writing a dummy instruction to emerge from sleep

mode, and wait at least one conversion cycle before

writing a start instruction.

50Hz/60Hz

With a 32,768Hz crystal, the 50Hz/60Hz bit sets the

integrate period equal to one line cycle for 50Hz/60Hz

environments. When D6 (in command input register 0)

is set to 0, the integrate count is an integer multiple of

60Hz (32,768Hz/60Hz = 546 counts). When D6 is set to

1, the integrate input count is an integer multiple of

50Hz (32,768Hz/50Hz = 655 counts). Achieve the

greatest AC rejection by adjusting the integration peri-

od for 50Hz or 60Hz.

Start Conversion Bit

The start conversion bit (D7) in command input register

0 initiates a conversion when set to 1. The MAX132

immediately starts a conversion, stops at conversion

end, and then waits for the next start-bit command. A

start instruction is needed to initiate each conversion.

To initiate a continuous data stream, write a separate

start command for each conversion in three ways:

1) Wait longer than a known conversion time and then

write another start command.

2) Poll either the EOC status register bit or the EOC

line to determine conversion end and start time for

the next conversion. EOC becomes 1 at conversion

end at count 0000 of the conversion counter (Figure

10).

3) Set the start bit to 1 before a conversion end. The

internal conversion counter is then checked for its

count. If the count is 0000 (EOC = 1), a new conver-

sion starts and the conversion counter is set to

0001. The start bit resets to 0 after 5 clock cycles.

The MAX132 will not check the start bit again until

the conversion counter returns to a 0000 count. This

means a start command can be given any time after

0005 internal conversion count; the next conversion

starts when the counter returns to 0000.

DE-1 DE-2 DE-3 DE-4X8-1 X8-2 X8-3 ZERO INT

ZERO INT

INT OUT

50Hz mode

INTEGRATE

264

545

655

38 145

679

MAX

545

MAX

SOFT

OVERRANGE

AREA

(SEE TEXT)

40 147

0001

0000

0111

INT START

RESET 60Hz

60Hz mode

659 667

CHOP

16001346 1638 1783 1823 1970 2017 2047 0000

RESET EVENTS

INTERNAL CONVERSION DATA LATCH

LATCH

EOC

Figure 10. Conversion Timing (Negative Input Shown)

MAX132

±18-Bit ADC with Serial Interface

12 ______________________________________________________________________________________

Command Input Register 1

User-Programmable Output Bits P0 to P3

Command input register 1 always has data bit D0 = 1.

Data bits D4 to D7 of command register 1 control the

states of the user-programmable output pins P0 to P3,

respectively (Table 2). These four outputs can be used

to control an external multiplexer, programmable gain

amplifier, or other devices.

Output Registers

Output data is the sum of system offset (read zero) plus

the results of the external input voltage measurement.

sion data. New data is available after EOC goes high.

Access register 0 by setting RS0 and RS1 to 0.

Data is in a twos-complement format‚ where the polarity

bit is a 1 for negative polarity data. Access register 1

by setting control bits RS0 = 1 and RS1 = 0 when writ-

ing to the command input register.

Status Register

Bits B0–B2

The B0, B1, and B2 bits are located in the status regis-

ter. At the end of each conversion these bits are updat-

ed and read back from the status register. For full

18-bit resolution, use bits B0–B2. Average multiple

results to increase accuracy. The polarity bit informa-

tion is necessary to determine if the reading is not in

overrange (Tables 4 and 5).

Integrate Bit

The integrate (INT) bit is set to 1 at the beginning of the

integration phase and becomes 0 at the end. Poll INT

to determine the earliest time the input can be changed

without affecting the conversion.

End-of-Conversion Bit

The end-of-conversion (EOC) bit signals conversion sta-

tus. If EOC is 1, the conversion is complete and the ADC

waits in zero-integrate mode at time = 0000 for the next

start instruction. A conversion cycle has 2048 counts.

EOC becomes 1 at count 0000 and 0 at count 0001.

Collision Bit

The collision bit warns the microprocessor (µP) that the

collision occurs if the internal result latches on the falling

edge of CS, causing the collision bit to be set to 1 on the

rising edge of the next CS. This occurs because these

two pulses are asynchronous. Once the status register is

Table 4. Overrange Values for

Resolution Used

Table 5. Output Values for 16-Bit

Resolution (Offset Corrected)

Bits

Used

B18–B3

B18–B2

B18–B1

Resolution

Bits

±15

±16

±17

B18–B0 ±18

Soft Overrange

Start Value

34,880

69,760

139,520

Hard Overrange

Maximum Value

43,805

87,610

175,220

279,040 350,440

Input

+640mV

+576mV

+545mV

Hexadecimal

Reading

+A000

+9000

+8840

Decimal

Counts

+40960*

+36864*

+34880*

+512mV

Comment

+8000

Positive Reference

Voltage

+32768 Positive Full Scale

+448mV

+384mV

+320mV

+7000

+6000

+5000

+28672

+24576

+20480

+256mV +4000 +16384

+192mV

+128mV

+15µV

+3000

+2000

+0001

+12288

+8192

0 +0000 0

-15µV

-64mV

-128mV

-FFFF

-F000

-E000

-1

-4096

-8192

-192mV -D000 -12288

-256mV

-320mV

-384mV

-C000

-B000

-A000

-16384

-20480

-24576

-448mV -9000 -28672

-512mV

-545mV

-576mV

-8000

-77C0

-7000

-32768

-34880*

-36864*

-640mV

Negative Full Scale

-6000

Negative Reference

Voltage

-40960*

+64mV +1000 +4096

* Soft Overrange Operation

Note: The MAX132 exhibits additional errors when operating

in the soft overrange area. Operation in this region is not

included in the specifications. The soft overrange values listed

in Table 5 do not include error correction.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX132CWG

Mfr. #:

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Manufacturer:

Maxim Integrated

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Analog to Digital Converters - ADC 18-Bit ADC with Serial Interface

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MAX132CWG

MAX132CWG

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