14
4952J–AUTO–03/11
Atmel ATA6836
7 Serial Interface: Logic Inputs DI, CLK, CS
7.1
Input voltage low-level
threshold
24-26 17-19 V
IL
0.3 ×
V
VCC
VA
7.2
Input voltage high-level
threshold
24-26 17-19 V
IH
0.7 ×
V
VCC
VA
7.3
Hysteresis of input
voltage
24-26 17-19 ΔV
I
50 500 mV A
7.4
Pull-down current pin
DI, CLK
V
DI
, V
CLK
= V
VCC
25, 26 18, 19 I
PDSI
250 µAA
7.5 Pull-up current pin CS V
CS
= 0V 24 17 I
PUSI
–50 –2 µA A
8 Serial Interface: Logic Output DO
8.1 Output voltage low level I
OL
= 3mA 18 13 V
DOL
0.5 V A
8.2
Output voltage high
level
I
OL
= –1mA 18 13 V
DOH
V
VCC
–
0.7V
VA
8.3
Leakage current
(tri-state)
V
CS
= V
VCC,
0V < V
DO
< V
VCC
18 13 I
DO
–10 10 µA A
7. Electrical Characteristics (Continued)
7.5V < V
S
< 40V; 4.75 < V
CC
< 5.25V; INH = High; –40°C < T
j
< 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters Test Conditions
Pin SO28 Pin QFN24
Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1ms.
8. Serial Interface: Timing
Parameters Test Conditions Pin SO28 QFN24
Number in
Timing
Diagram
(Figure 8-1
on page 15) Symbol Min. Typ. Max. Unit
DO enable after CS
falling edge
C
DO
= 100pF 18 13 1 t
ENDO
200 ns
DO disable after CS
rising edge
C
DO
= 100pF 18 13 2 t
DISDO
200 ns
DO fall time C
DO
= 100pF 18 13 - t
DOf
100 ns
DO rise time C
DO
= 100pF 18 13 - t
DOr
100 ns
DO valid time C
DO
= 100pF 18 13 10 t
DOVal
200 ns
CS setup time 24 17 4 t
CSSethl
225 ns
CS setup time 24 17 8 t
CSSetlh
225 ns
CS high time Input register bit 14 (SCT) = high 24 17 9 t
CSh
17 ms
CS high time Input register bit 14 (SCT) = low 24 17 9 t
CSh
2.1 ms
CLK high time 25 18 5 t
CLKh
225 ns
CLK low time 25 18 6 t
CLKl
225 ns
CLK period time 25 18 - t
CLKp
500 ns
CLK setup time 25 18 7 t
CLKSethl
225 ns
CLK setup time 25 18 3 t
CLKSetlh
225 ns
DI setup time 26 19 11 t
DIset
40 ns
DI hold time 26 19 12 t
DIHold
40 ns
