OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

570BLFT

P1-P3P4-P6P7-P9P10-P11
DATASHEET
MULTIPLIER AND ZERO DELAY BUFFER ICS570
IDT™ / ICS™
MULTIPLIER AND ZERO DELAY BUFFER 1
ICS570 REV K 073007
Description
The ICS570 is a high-performance Zero Delay Buffer (ZDB)
which integrates IDT’s proprietary analog/digital Phase
Locked Loop (PLL) techniques. The A version is
recommended for 5 V designs and the B version for
3.3 V designs. The chip is part of IDT’s ClockBlocks
TM
family, and was designed as a performance upgrade to
meet today’s higher speed and lower voltage requirements.
The zero delay feature means that the rising edge of the
input clock aligns with the rising edges of both output
clocks, giving the appearance of no delay through the
device. There are two outputs on the chip, one being a
low-skew divide by two of the other output. The device
incorporates an all-chip power down/tri-state mode that
stops the internal PLL and puts both outputs into a high
impedance state.
The ICS570 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to graphics/video. By allowing off-chip
feedback paths, the device can eliminate the delay through
other devices.
The ICS570 A and B versions were designed to improve
input to output jitter from the original ICS570M version, and
are recommended for all new designs.
Features
• 8-pin SOIC package
• Available in Pb (lead) free package
• Pin-for-pin replacement and upgrade to ICS570M
• Functional equivalent to AV9170 (not a pin-for-pin
replacement)
• Low input to output skew of 300 ps max (>60 MHz
outputs)
• Ability to choose between 14 different multipliers from
0.5x to 32x
• Output clock frequency up to 170 MHz at 3.3 V
• Can recover degraded input clock duty cycle
• Output clock duty cycle of 45/55
• Power Down and Tri-State Mode
• Passes spread spectrum clock modulation
• Full CMOS clock swings with 25 mA drive capability at
TTL levels
• Advanced, low power CMOS process
• ICS570B has an operating voltage of 3.3 V (±5%)
• ICS570A has an operating voltage of 5.0 V (±5%)
• Industrial temperature version available
Block Diagram
Phase
Detector,
Charge
Pump,
and Loop
Filter
divide
by N
CLK
External feedback can come from CLK or CLK/2 (see table on page 2)
ICLK
FBIN
S1:0
VCO
CLK
2
/2
ICS570
MULTIPLIER AND ZERO DELAY BUFFER ZDB AND MULTIPLIER
IDT™ / ICS™
MULTIPLIER AND ZERO DELAY BUFFER 2
ICS570 REV K 073007
Pin Assignment
Clock Multiplier Decoding Table
(Multiplies Input clock by amount shown)
0 = connect directly to ground
M = leave unconnected (self-biases to VDD/2)
1 = connect directly to VDD
*Input range with CLK feedback is double that for CLK/2
S1
VDD
GND
CLK
ICLK
S0
FBIN
CLK/21
2
3
4
8
7
6
5
S1
VDD
GND
CLK
ICLK
S0
FBIN
CLK/21
2
3
4
8
7
6
5
8 pin (150 mil) SOIC
S1 S0
FBIN from
CLK
FBIN from
CLK/2
ICS570B (3.3 V) ICS570A (5.0 V)
CLK CLK/2 CLK CLK/2 ICLK Input Range FB from CLK/2* ICLK Input Range FB from CLK/2*
#1 #6 pin #7 pin #8 pin #7 pin #8
0 0 Power Down and Tri-State - -
0 M x3 x1.5 x6 x3 3.75 to 28 2.5 to 25
0 1 x4 x2 x8 x4 2.75 to 19 2.5 to 19
M 0 x8 x4 x16 x8 2.5 to 9.5 2.5 to 9.5
M M x6 x3 x12 x6 2.5 to 12.5 2.5 to 12.5
M 1 x10 x5 x20 x10 2.5 to 7.5 2.5 to 7.5
1 0 x1 /2 x2 x1 11 to 85 5 to 75
1 M x16 x8 x32 x16 1.5 to 5 1.5 to 5
1 1 x2 x1 x4 x2 5.5 to 37.5 2.5 to 37.5
ICS570
MULTIPLIER AND ZERO DELAY BUFFER ZDB AND MULTIPLIER
IDT™ / ICS™
MULTIPLIER AND ZERO DELAY BUFFER 3
ICS570 REV K 073007
Pin Descriptions
External Components
The ICS570 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be connected
close to the part to minimize lead inductance. No external power supply filtering is required for this device. A 33Ω
series terminating resistor can be used next to each output pin.
Recommended Circuit
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 S1 Input Select 1 for output clock. Connect to GND, VDD, or float per decoding
2 VDD Power Connect to +3.3 V (ICS570B). Connect to +5.0 V (ICS570A).
3 GND Power Connect to ground.
4 ICLK Input Reference clock input.
5 FBIN Input Feedback clock input.
6 S0 Input Select 0 for output clock. Connect to GND, VDD, or float per decoding
7 CLK Output Clock output per table above.
8 CLK/2 Output Clock output per table above. Low skew divide by two of pin 7 clock.
CLK
CLK/2
FBIN
S1
VDD
GND
Input
S0
ICLK
x2 Mode (S1, S0 = 1, 1)
CLK Feedback
CLK
CLK/2
ICLK
x2 Mode (S1, S0 = 1, 0)
CLK/2 Feedback
CLK
CLK/2
P1-P3P4-P6P7-P9P10-P11

570BLFT

Mfr. #:
Buy 570BLFT
Manufacturer:
IDT
Description:
Clock Buffer MULTIPLIER AND ZERO DELAY BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet