Data Sheet AD8029/AD8030/AD8040
Rev. B | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4. AD8029/AD8030/AD8040 Stress Ratings
Supply Voltage 12.6 V
Power Dissipation See Figure 6
Common-Mode Input Voltage ±V
S
± 0.5 V
Differential Input Voltage ±1.8 V
Storage Temperature –65°C to +125°C
Operating Temperature Range –40°C to +125°C
Lead Temperature Range
(Soldering 10 sec)
300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8029/AD8030/
AD8040 package is limited by the associated rise in junction
temperature (T
J
) on the die. The plastic encapsulating the die
locally reaches the junction temperature. At approximately
150°C, which is the glass transition temperature, the plastic
changes its properties. Even temporarily exceeding this
temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric
performance of the AD8029/AD8030/AD8040. Exceeding a
junction temperature of 175°C for an extended period can
result in changes in silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (θ
JA
),
ambient temperature (T
A
), and the total power dissipated in the
package (P
D
) determine the junction temperature of the die.
The junction temperature can be calculated as
T
J
= T
A
+ (P
D
× θ
JA
)
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). Assuming the load (R
L
) is referenced to
midsupply, the total drive power is V
S
/2 × I
OUT
, some of which is
dissipated in the package and some in the load (V
OUT
× I
OUT
).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
P
D
= Quiescent Power + (Total Drive Power – Load Power)
( )
L
OUT
L
OUTS
SS
D
R
V
R
V
V
IVP
2
–
2
×+×=
RMS output voltages should be considered. If R
L
is referenced to
V
S
–, as in single-supply operation, then the total drive power is
V
S
× I
OUT
.
If the rms signal levels are indeterminate, consider the worst
case, when V
OUT
= V
S
/4 for R
L
to midsupply:
( )
( )
L
S
SS
D
R
V
IVP
2
4/
+×=
In single-supply operation with R
L
referenced to V
S
–, worst case
is V
OUT
= V
S
/2.
Airflow increases heat dissipation, effectively reducing θ
JA
. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduce
the θ
JA
. Care must be taken to minimize parasitic capacitances
at the input leads of high speed op amps, as discussed in the
PCB Layout section.
Figure 6 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC-8
(125°C/W), SOT23-8 (160°C/W), SOIC-14 (90°C/W),
TSSOP-14 (120°C/W), and SC70-6 (208°C/W) packages on a
JEDEC standard 4-layer board. θ
JA
values are approximations.
–40 –20–10–30 0 10 20 30 40 50 60 70 80 90 100 110120
2.5
MAXIMUM POWER DISSIPATION (W)
1.0
0.5
1.5
2.0
0
AMBIENT TEMPERATURE (°C)
SOIC-8
TSSOP-14
SOIC-14
SOT-23-8
SC70-6
03679-A-018
Figure 6. Maximum Power Dissipation
Output Short Circuit
Shorting the output to ground or drawing excessive current
from the AD8029/AD8030/AD8040 could cause catastrophic
failure.
ESD CAUTION
