SL28SRC01BZI

PCI Express Gen 2 & Gen 3 Clock Generator
SL28SRC01
DOC#: SP-AP-0015 (Rev. 0.2) Page 1 of 11
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com
Features
Low power PCI Express Gen 2 & Gen 3clock generator
One100-MHz differential SRC clocks
Low power push-pull output buffers (no 50ohm to
ground needed)
Integrated 33ohm series termination resistors
Low jitter (<50pS)
SSON input for enabling spread spectrum clock
Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
Input frequency of 14.318MHz
Industrial Temperature -40
o
C to 85
o
C
3.3V power supply
16-pin TSSOP package
Pin Configuration
Block Diagram
SL28SRC01
DOC#: SP-AP-0015 (Rev. 0.2) Page 2 of 11
Pin Definitions
The SL28SRC01 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal causes the
SL28SRC01 to operate at the wrong frequency and violates
the ppm specification. For most applications there is a
300-ppm frequency shift between series and parallel crystals
due to incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, use the total capac-
itance the crystal sees to calculate the appropriate capacitive
loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
Pin No.
Name Type Description
1 XIN I 14.318 MHz Crystal input.
2 VDD PWR 3.3V power supply
3 VDD PWR 3.3V power supply
4 VSS GND Ground
5 VDD PWR 3.3V power supply
6 VSS GND Ground
7 SRC1 O, DIF 100 MHz Differential serial reference clocks.
8 SRC1# O, DIF 100 MHz Differential serial reference clocks.
9 VSS GND Ground
10 VDD PWR 3.3V power supply
11 VDD PWR 3.3V power supply
12 VSS GND Ground
13 VDD PWR 3.3V power supply
14 SSON I 3.3V LVTTL input for enabling spread spectrum clock
0 = Disable, 1 = Enable (-0.5% SS)
Extrenal 10K ohm pull-up or pull-down resistor required
15 VSS GND Ground
16 XOUT O 14.318 MHz Crystal output.
Table 1. Crystal Recommendations
Frequency
(Fund) Cut Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz AT Parallel 20 pF 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm
Figure 1. Crystal Capacitive Clarification
SL28SRC01
DOC#: SP-AP-0015 (Rev. 0.2) Page 3 of 11
capacitors are calculated to provide equal capacitive loading
on both sides.
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2 .
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires, etc.)
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8pF
Trim
33pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
F
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
V
DD
Core Supply Voltage 4.6 V
V
IN
Input Voltage Relative to V
SS
–0.5 4.6 V
DC
T
S
Temperature, Storage Non-functional –65 150 °C
T
A (commercial)
Temperature, Operating
Ambient, Commercial
Functional 0 85 °C
T
A (industrial)
Temperature, Operating
Ambient, Industrial
Functional -40 85 °C
T
J
Temperature, Junction Functional 150 °C
Ø
JC
Dissipation, Junction to Case JEDEC (JESD 51) 20 °C/
W
Ø
JA
Dissipation, Junction to Ambient JEDEC (JESD 51) 60 °C/
W
ESD
HBM
ESD Protection (Human Body
Model)
JEDEC (JESD 22 - A114) 2000 V
UL-94 Flammability Rating UL (Class) V–0
DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VDD 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
V
IH
3.3V Input High Voltage 2.0 V
DD
+ 0.3 V
V
IL
3.3V Input Low Voltage V
SS
– 0.3 0.8 V
I
IH
Input High Leakage Current Except internal pull-down resistors, 0 < V
IN
<
V
DD
–5A
I
IL
Input Low Leakage Current Except internal pull-up resistors, 0 < V
IN
< V
DD
–5 A
V
OH
3.3V Output High Voltage I
OH
= –1 mA 2.4 V
V
OL
3.3V Output Low Voltage I
OL
= 1 mA 0.4 V
I
OZ
High-impedance Output
Current
–10 10 A

SL28SRC01BZI

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products PCIe clock g., Xin(14M) -->1 PCIe out (gen.3)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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