© Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. 5
1 Publication Order Number:
NLSX4014/D
NLSX4014
4-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX4014 is a 4−bit configurable dual−supply bidirectional
level translator without a direction control pin. The I/O V
CC
− and I/O
V
L
−ports are designed to track two different power supply rails, V
CC
and V
L
respectively. The V
CC
supply rail is configurable from 1.3 V
to 4.5 V while the V
L
supply rail is configurable from 0.9 V to (V
CC
− 0.4) V. This allows lower voltage logic signals on the V
L
side to be
translated into higher voltage logic signals on the V
CC
side, and
vice−versa. Both I/O ports are auto−sensing; thus, no direction pin is
required.
The Output Enable (EN) input, when Low, disables both I/O ports
by putting them in 3−state. This significantly reduces the supply
currents from both V
CC
and V
L
. The EN signal is designed to track
V
L
.
Features
Wide High−Side V
CC
Operating Range: 1.3 V to 4.5 V
Wide Low−Side V
L
Operating Range: 0.9 V to (V
CC
− 0.4) V
Power Supply Isolation
All Outputs are in the High Impedance State if Either V
L
or V
CC
is at Ground
High−Speed with 100 Mb/s Guaranteed Date Rate for V
L
> 1.6 V
Low Bit−to−Bit Skew
Overvoltage Tolerant Enable and I/O Pins
Non−preferential Powerup Sequencing
Small packaging: 1.7 mm x 2.0 mm UQFN12
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
Typical Applications
Mobile Phones, PDAs, Other Portable Devices
www.onsemi.com
UQFN12
MU SUFFIX
CASE 523AE
MARKING
DIAGRAMS
WAMG
G
1
Device Package Shipping
ORDERING INFORMATION
NLSX4014MUTAG UQFN12
(Pb−Free)
3000/Tape & Ree
l
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NLSX4014DR2G SO−14
(Pb−Free)
2500/Tape & Ree
l
NLSX4014DTR2G TSSOP14
(Pb−Free)
2500/Tape & Ree
l
SOIC−14
D SUFFIX
CASE 751A
1
4
1
NLSX4014G
AWLYWW
1
14
TSSOP−14
DT SUFFIX
CASE 948G
14
1
NLSX
4014
ALYWG
G
1
14
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
WA = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
NLVSX4014MUTAG UQFN12
(Pb−Free)
3000/Tape & Ree
l
NLSX4014
www.onsemi.com
2
Figure 1. Pin Assignments
13
14
12
11
10
9
8
2
1
3
4
5
6
7
Figure 2. Logic Diagram
1
2
3
4
5
11
10
9
8
7
12
6
I/O V
L
1
I/O V
L
2
I/O V
L
3
I/O V
L
4
V
CC
I/O V
CC
1
I/O V
CC
2
I/O V
CC
3
I/O V
CC
4
V
L
EN
GND
(Top View)
V
L
V
CC
GND
EN
I/O V
L
1
I/O V
L
2
I/O V
L
3
I/O V
L
4
I/O V
CC
1
I/O V
CC
2
I/O V
CC
3
I/O V
CC
4
I/O V
L
1
I/O V
L
2
I/O V
L
3
I/O V
L
4
V
CC
I/O V
CC
1
I/O V
CC
2
I/O V
CC
3
I/O V
CC
4
V
L
EN
GND
NC
NC
PIN ASSIGNMENT
Pins Description
V
CC
V
CC
Input Voltage
V
L
V
L
Input Voltage
GND Ground
EN Output Enable
I/O V
CC
n I/O Port, Referenced to V
CC
I/O V
L
n I/O Port, Referenced to V
L
FUNCTION TABLE
EN Operating Mode
L Hi−Z
H I/O Buses Connected
NLSX4014
www.onsemi.com
3
Figure 3. Typical Application Circuit
I/O V
L
1
I/O V
L
n
ENEN
I/On
I/O1
GND
+1.8 V System
+1.8V +3.6V
+3.6 V System
I/On
I/O1
GNDGND
NLSX4014
I/O V
CC
1
I/O V
CC
n
V
L
V
CC
Figure 4. Simplified Functional Diagram (1 I/O Line)
(EN = 1)
P
One−Shot
N
One−Shot
P
One−Shot
N
One−Shot
V
L
I/O V
L
I/O V
CC
V
CC
4 kW
4 kW

NLSX4014DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Translation - Voltage Levels 4 BIT TRANSLATOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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