CY8C9520A
CY8C9540A
CY8C9560A
Document Number: 38-12036 Rev. *I Page 28 of 32
microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal The reference to a circuit containing both analog and digital techniques and components.
modulator A device that imposes a signal on a carrier.
noise 1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator A circuit that may be crystal controlled and is used to generate a clock frequency.
parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware
reset.
PSoC
®
Cypress Semiconductor’s PSoC
®
is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
modulator (PWM)
An output in the form of duty cycle which varies as a function of the applied measurand
RAM An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register A storage device with a specific capacity, such as a bit or byte.
reset A means of bringing a system back to a know state. See hardware reset and software reset.
ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial 1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
Glossary (continued)
CY8C9520A
CY8C9540A
CY8C9560A
Document Number: 38-12036 Rev. *I Page 29 of 32
stop bit A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
V
DD
A name for a power net meaning “voltage drain.” The most positive power supply signal. Usually 5 V or 3.3 V.
V
SS
A name for a power net meaning “voltage source.” The most negative power supply signal.
watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Glossary (continued)
CY8C9520A
CY8C9540A
CY8C9560A
Document Number: 38-12036 Rev. *I Page 30 of 32
Errata
This section describes the errata for CY8C9560A device. Details include the trigger condition, scope of impact, available workaround,
and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Qualification Status
CY8C9560A Rev. A – In Production
Errata Summary
The following table defines the errata applicability to available devices.
1. The command 01h cannot store more than128 bytes of configuration data from SRAM to EEPROM.
Problem Definition
The Store Config to E
2
POR Defaults Cmd (01h) can write only up to 128 bytes of configuration data from SRAM to the EEPROM.
Configuration data exceeding 128 bytes are ignored.
Parameters Affected
NA
Trigger Condition
NA
Scope of Impact
Configuration data from SRAM to EEPROM exceeding 128 bytes are ignored.
Workaround
As a workaround, use the Write E
2
POR Defaults Cmd (03h) command to explicitly write all configuration data to EEPROM
using I
2
C.
Fix Status
No fixes are planned. You must use the recommended workaround.
Part Number
CY8C9560A
Items Part Number Silicon Revision Fix Status
1. The command 01h cannot store more
than128 bytes of configuration data from
SRAM to EEPROM.
CY8C9560A A No silicon fix planned.
Workaround is required.

CY8C9560A-24AXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Interface - I/O Expanders 60BIT IO EXPANDER W/EEPROM 27Kb
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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