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74LVC161284TTR

P1-P3P4-P6P7-P9P10-P11
74LVC161284
4/11
DC SPECIFICATIONS
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
V
CCcable
(V)
-40 to 85 °C
Min. Max.
V
IH
High Level
Input Voltage
An, Bn, PL
IN
, DIR, HD
3.0
to
3.6
3.0
to
5.5
2
VCn 2.3
HL
IN
2.6
V
IL
Low Level
Input Voltage
An, Bn, PL
IN
, DIR, HD
0.8
VCn 0.8
HL
IN
1.6
V
OH
High Level
Output Voltage
An, HL
3.0 3.0
I
O
=-50µA
2.8
V
3.0 3.0
I
O
=-4mA
2.4
Bn, Yn 3.0 3.0
I
O
=-14mA
2.0
Bn, Yn 3.0 4.5
I
O
=-14mA
2.23
PL 3.15 3.15
I
O
=-500µA
3.1
V
OL
Low Level
Output Voltage
An, HL
3.0 3.0
I
O
=50µA
0.2
V
3.0 3.0
I
O
=4mA
0.4
Bn, Yn 3.0 3.0
I
O
=14mA
0.8
Bn, Yn 3.0 4.5
I
O
=14mA
0.77
PL 3.0 3.0
I
O
=84mA
0.95
PL 3.0 4.5
I
O
=84mA
0.90
I
I
Input Current Cn
3.6 3.6
V
I
=V
CC
50 µA
3.6 3.6
V
I
=GND (Pull-up res)
-3.5 mA
All input except B or C
3.6 5.0
V
I
=V
CC
or GND
± 1 µA
I
CC
Quiescent Supply Current
3.6 5.0
V
I
=V
CC
I
O
=0
0.8
mA
V
I
=GND (12xPull-up)
45
I
OZ
High
Impedance
Output
Leakage
Current
Bn
3.6 5.0
V
O
=V
CC
20 µA
3.6 3.6
V
O
=GND (Pull-up res)
-3.5 mA
A1-A8
3.6 5.0
V
O
=V
CC
or GND
± 20 µA
Open Drain Y Output
3.6 3.6
V
O
=GND (Pull-up res)
-3.5 mA
I
OFF
Power Off
Leakage
Current
B, Y output (to GND)
0 5.0
V
I
or V
O
=0to7V
100 µA
B, Y output (to V
CC
)
0 5.0
V
I
or V
O
=0to7V
10 µA
V
hys
Input
Hysteresis
An, Bn, PL
IN
, DIR, HD
3.3 5.0 0.4
VCn 3.3 5.0 0.8
HL
IN
3.3 5.0 0.2
Z
O
Output
Impedance
B1-B8, Y9-Y13 3.3 5.0
V
B
=V
OH
30 55 Ω
R
P
Pull-up
Resistance
B1-B8, Y9-Y13,
C14-C17
3.3 5.0
V
B
=V
OH
1150 1650 Ω
74LVC161284
5/11
AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device
switching in the same direction, either HIGH or LOW (t
OSLH
=|t
PLHm
-t
PLHn
|, t
OSHL
=|t
PHLm
-t
PHLn
|
2) Parameter guaranteed by design
CAPACITANCE CHARACTERISTICS
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
V
CCcable
(V)
-40 to 85 °C
Min. Max.
t
PLH
t
PHL
Propagation
Delay Time
A1-A8 to B1-B8,
A9-A13 to Y9-Y13
3.0
to
3.6
3.0
to
5.5
R
L
=500Ω C
L
=50pF
1 7.5 ns
B1-B8 to A1-A8,
C14-C17 to A14-A17
R
L
=500Ω C
L
=50pF
1 9.0 ns
PL
IN
to PL
OUT
R
L
=500Ω C
L
=50pF
1 7.0 ns
HL
IN
to HL
OUT
R
L
=500Ω C
L
=50pF
1 11.0 ns
t
PZH
t
PZL
Enable Delay
Time
DIR to A 3.0
to
3.6
3.0
to
5.5
R
L
=500Ω C
L
=50pF
112ns
HD to Bn, Y9-Y13
R
L
=500Ω C
L
=50pF
1 8.5 ns
t
PLZ
t
PHZ
Disable Delay
Time
DIR to A
3.0
to
3.6
3.0
to
5.5
R
L
=500Ω C
L
=50pF
1 8.5 ns
DIR to A R
L
=500Ω C
L
=50pF
1 8.5 ns
HD to Bn, Y9-Y13 R
L
=500Ω C
L
=50pF
1 8.5 ns
t
r
t
f
Rise and Fall Time
B1-B8, Y9-Y13 Open Drain
3.0
to
3.6
3.0
to
5.5
R
L
=500Ω C
L
=50pF
1 120 ns
t
OSLH
t
OSHL
Output To Output Skew Time (note1, 2) 3.0
to
3.6
3.0
to
5.5
R
PULL-UP
=500Ω
C
L
=50pF
12ns
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
V
CC/CABLE
(V)
T
A
=25°C
Min. Typ. Max.
C
IN
Control Input Capacitance
(HD, DIR, A9-A13, C14-C17,
PL
IN
,HL
IN
)
Open Open 4 pF
C
I/O
I/O Pin Capacitance
3.3 5.0 6 pF
74LVC161284
6/11
TEST CIRCUIT
C
L
= 50 pF or equivalent (includes jig and probe capacitance)
R
L
=R1=500Ω or equivalent
R
T
=Z
OUT
of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAY INPUT An TO OUTPUT (f=1MHz; 50% duty cycle)
TEST S1S2S3
t
PHL
(A1-A8 to B1-B8, A9-A13 to Y9-Y13, PLH
IN
to PLH) (see waveform 1)
Open
V
CC
V
CC
t
PLH
(A1-A8 to B1-B8, A9-A13 to Y9-Y13, PLH
IN
to PLH, HD to B1-B8, Y9-Y13, PLH)
(see waveform 1)
Open GND GND
t
PHL
,t
PLH
(B1-B8 to A1-A8, C14-C17 to A14-A17, HLH
IN
to HLH) (see waveform 2)
Open
GND GND
t
r
,t
f
(A1-A8 to B1-B8, A9-A13 to Y9-Y13) (see waveform 1)
Open
V
CC
GND
t
PLZ
(DIR to A1-A8) (see waveform 4) 6V GND GND
t
PHZ
(DIR to A1-A8) (see waveform 4)
Open
GND GND
t
PZL
(DIR to A1-A8) (see waveform 3) 1.4V GND GND
t
PZH
(DIR to A1-A8) (see waveform 3) 4.4V GND GND
t
PLZ
(DIR to B1-B8) (see waveform 4) 6V GND GND
t
PHZ
(DIR to B1-B8) (see waveform 4)
Open
GND GND
P1-P3P4-P6P7-P9P10-P11

74LVC161284TTR

Mfr. #:
Buy 74LVC161284TTR
Manufacturer:
STMicroelectronics
Description:
Bus Transceivers Hi-Spd IEEE1284 Tran
Lifecycle:
New from this manufacturer.
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