AD7691-EP Enhanced Product
Rev. A | Page 6 of 13
VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, V
REF
= VDD, all specifications T
MIN
to T
MAX
, unless otherwise noted. See Figure 3 and Figure 4
for load conditions.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
CONV
0.5 3.7 μs
Acquisition Time t
ACQ
1.8 μs
Time Between Conversions t
CYC
5.5 μs
CNV Pulse Width (CS Mode)
t
CNVH
10 ns
SCK Period (CS Mode)
t
SCK
25 ns
SCK Period (Chain Mode) t
SCK
VIO Above 3 V 29 ns
VIO Above 2.7 V 35 ns
VIO Above 2.3 V 40 ns
SCK Low Time t
SCKL
12 ns
SCK High Time t
SCKH
12 ns
SCK Falling Edge to Data Remains Valid t
HSDO
5 ns
SCK Falling Edge to Data Valid Delay t
DSDO
VIO Above 3 V 24 ns
VIO Above 2.7 V 30 ns
VIO Above 2.3 V 35 ns
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
t
EN
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
t
DIS
25 ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
t
SSDICNV
30 ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
t
HSDICNV
0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SSCKCNV
5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
HSCKCNV
8 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SSDISCK
8 ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
HSDISCK
10 ns
SDI High to SDO High (Chain Mode with Busy Indicator) t
DSDOSDI
36
Timing Diagrams
500µA I
OL
500µA I
OH
1.4V
TO SDO
C
L
50pF
12156-002
Figure 3. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
t
DELAY
t
DELAY
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
12156-003
Figure 4. Voltage Levels for Timing
