LTC2460/LTC2462
17
24602fa
applicaTions inForMaTion
There is a limit to how large R
S
• C
IN
should be for a given
application. Increasing R
S
beyond a given point increases
the voltage drop across R
S
due to the input current,
to the point that significant measurement errors exist.
Additionally, for some applications, increasing the R
S
• C
IN
product too much may unacceptably attenuate the signal
at frequencies of interest.
For most applications, it is desirable to implement C
IN
as
a high-quality 0.1µF ceramic capacitor and R
S
≤ 1k. This
capacitor should be located as close as possible to the
actual V
IN
package pin. Furthermore, the area encompassed
by this circuit path, as well as the path length, should be
minimized.
In the case of a 2-wire sensor that is not remotely
grounded, it is desirable to split R
S
and place series
resistors in the ADC input line as well as in the sensor
ground return line, which should be tied to the ADC GND
pin using a star connection topology.
Figure 17 shows the measured LTC2462 INL vs Input
Voltage as a function of R
S
value with an input capacitor
C
IN
= 0.1µF.
In some cases, R
S
can be increased above these guidelines.
The input current is zero when the ADC is either in sleep
or I/O modes. Thus, if the time constant of the input RC
circuit t = R
S
• C
IN
, is of the same order of magnitude or
longer than the time periods between actual conversions,
then one can consider the input current to be reduced
correspondingly.
These considerations need to be balanced out by the input
signal bandwidth. The 3dB bandwidth ≈ 1/(2pR
S
C
IN
).
Finally, if the recommended choice for C
IN
is unacceptable
for the user’s specific application, an alternate strategy is to
eliminate C
IN
and minimize C
PAR
and R
S
. In practical terms,
this configuration corresponds to a low impedance sensor
directly connected to the ADC through minimum length
traces. Actual applications include current measurements
through low value sense resistors, temperature measure-
ments, low impedance voltage source monitoring, and so
on. The resultant INL vs V
IN
is shown in Figure 18. The
measurements of Figure 18 include a capacitor C
PAR
cor-
responding to a minimum sized layout pad and a minimum
width input trace of about 1 inch length.
Signal Bandwidth, Transition Noise and Noise
Equivalent Input Bandwidth
The LTC2460/LTC2462 include a sinc
1
type digital filter
with the first notch located at f
0
= 60Hz. As such, the
3dB input signal bandwidth is 26.54Hz. The calculated
LTC2460/LTC2462 input signal attenuation vs frequency
over a wide frequency range is shown in Figure 19. The
calculated LTC2460/LTC2462 input signal attenuation vs
frequency at low frequencies is shown in Figure 20. The
converter noise level is about 2.2µV
RMS
and can be mod-
eled by a white noise source connected at the input of a
noise-free converter.
On a related note, the LTC2462 uses two separate A/D
converters to digitize the positive and negative inputs. Each
of these A/D converters has 2.2µV
RMS
transition noise.
If one of the input voltages is within this small transition
noise band, then the output will fluctuate one bit, regard-
less of the value of the other input voltage. If both of the
input voltages are within their transition noise bands, the
output can fluctuate 2 bits.
For a simple system noise analysis, the V
IN
drive circuit can
be modeled as a single-pole equivalent circuit character-
ized by a pole location f
i
and a noise spectral density n
i
.
If the converter has an unlimited bandwidth, or at least a
bandwidth substantially larger than f
i
, then the total noise
contribution of the external drive circuit would be:
V
n
= n
i
p / 2 • f
i
Then, the total system noise level can be estimated as
the square root of the sum of (V
n
2
) and the square of the
LTC2460/LTC2462 noise floor (~2.2µV
2
).
