LTC2460/LTC2462
15
24602fa
applicaTions inForMaTion
PRESERVING THE CONVERTER ACCURACY
The LTC2460/LTC2462 are designed to minimize the conver-
sion result’s sensitivity to device decoupling, PCB layout,
antialiasing circuits, line and frequency perturbations.
Nevertheless, in order to preserve the high accuracy capa-
bility of this part, some simple precautions are desirable.
Digital Signal Levels
Due to the nature of CMOS logic, it is advisable to keep input
digital signals near GND or V
CC
. Voltages in the range of
0.5V to V
CC
– 0.5V may result in additional current leakage
from the part. Undershoot and overshoot should also be
minimized, particularly while the chip is converting. It is
thus beneficial to keep edge rates of about 10ns and limit
overshoot and undershoot to less than 0.3V.
Noisy external circuitry can potentially impact the output
under 2-wire operation. In particular, it is possible to get
the LTC2460/LTC2462 into an unknown state if an SCK
pulse is missed or noise triggers an extra SCK pulse.
In this situation, it is impossible to distinguish SDO = 1
(indicating conversion in progress) from valid “1” data
bits. As such, CPOL = 1 is recommended for the 2-wire
mode. The user should look for SDO = 0 before reading
data, and look for SDO = 1 after reading data. If SDO does
not return a “0” within the maximum conversion time (or
return a “1” after a full data read), generate 16 SCK pulses
to force a new conversion.
Driving V
CC
and GND
In relation to the V
CC
and GND pins, the LTC2460/LTC2462
combines internal high frequency decoupling with damping
elements, which reduce the ADC performance sensitivity
to PCB layout and external components. Nevertheless,
the very high accuracy of this converter is best pre-
served by careful low and high frequency power supply
decoupling.
A 0.1µF, high quality, ceramic capacitor in parallel with
a 10µF low ESR ceramic capacitor should be connected
between the V
CC
and GND pins, as close as possible to the
package. The 0.1µF capacitor should be placed closest to
the ADC package. It is also desirable to avoid any via in the
circuit path, starting from the converter V
CC
pin, passing
through these two decoupling capacitors, and returning
to the converter GND pin. The area encompassed by this
circuit path, as well as the path length, should be minimized.
As shown in Figure 15, REF
–
is used as the negative refer-
ence voltage input to the ADC. This pin can be tied directly
to ground or kelvined to sensor ground. In the case where
REF
–
is used as a sense input, it should be bypassed to
ground with a 0.1μF ceramic capacitor in parallel with a
10μF low ESR ceramic capacitor.
Very low impedance ground and power planes, and star
connections at both V
CC
and GND pins, are preferable. The
V
CC
pin should have two distinct connections: the first to
the decoupling capacitors described above, and the second
to the ground return for the power supply voltage source.
REFOUT and COMP
The on chip 1.25V reference is internally tied to the con-
verter’s reference input and is output to the REFOUT pin.
A 0.1μF capacitor should be placed on the REFOUT pin.
It is possible to reduce this capacitor, but the transition
Figure 15. LTC2460/LTC2462 Analog Input/Reference
Equivalent Circuit
R
SW
15k
(TYP)
I
LEAK
I
LEAK
V
CC
V
CC
V
CC
V
CC
C
EQ
0.35pF
(TYP)
IN
+
IN
–
REF
–
REFOUT
INTERNAL
REFERENCE
24602 F15
R
SW
15k
(TYP)
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
LEAK
I
LEAK
