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LTC2462IMS#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LTC2460/LTC2462
10
24602fa
applicaTions inForMaTion
The LTC2460 (single-ended input) output code is a direct
binary encoded result, see Table 1.
During the data output operation the CS input pin must
be pulled low (CS = LOW). The data output process starts
with the most significant bit of the result being present at
the SDO output pin (SDO = D15) once CS goes low. A new
data bit appears at the SDO output pin after each falling
edge detected at the SCK input pin. The output data can
be reliably latched on the rising edge of SCK.
Data Input Format
The data input word is 4 bits long and consists of two en-
able bits (EN1 and EN2) and two programming bits (SPD
and SLP). EN1 is applied to the first rising edge of SCK
after the conversion is complete. Programming is enabled
by setting EN1 = 1 and EN2 = 0.
The speed bit (SPD) is only used by the LTC2460. In the
default mode, SPD = 0, the output rate is 60Hz and con-
tinuous background offset calibration is not performed. By
changing the SPD bit to 1, background offset calibration is
performed and the output rate is reduced to 30Hz. Alterna-
tively, SDI can be tied directly to ground (SPD = 0) or V
CC
(SPD = 1), eliminating the need to program the device. The
LTC2462 data output rate is always 60Hz and background
offset calibration is performed (SPD = don’t care).
The sleep bit (SLP) is used to power down the on chip
reference. In the default mode, the reference remains
powered up even when the ADC is powered down. If the
SLP bit is set HIGH, the reference will power down after
the next conversion is complete. It will remain powered
down until CS is pulled low. The reference startup time
is approximately 12ms. In order to ensure a stable refer-
ence for the following conversions, either the data input/
output time should be delayed 12ms after CS goes low or
the first conversion following a reference start up should
be discarded. If SDI is tied HIGH (LTC2460 operating in
30Hz mode) the SLP mode is disabled.
Conversion Status Monitor
For certain applications, the user may wish to monitor the
LTC2460/LTC2462 conversion status. This can be achieved
by holding SCK HIGH during the conversion cycle. In
this condition, whenever the CS input pin is pulled low
(CS = LOW), the SDO output pin will provide an indication
of the conversion status. SDO = HIGH is an indication of
a conversion cycle in progress while SDO = LOW is an
indication of a completed conversion cycle. An example
of such a sequence is shown in Figure 5.
Conversion status monitoring, while possible, is not re-
quired for the LTC2460/LTC2462 as its conversion time is
fixed and typically 16.6ms (23ms maximum). Therefore,
external timing can be used to determine the completion of a
conversion cycle.
SERIAL INTERFACE
The LTC2460/LTC2462 transmit the conversion result and
receive the start of conversion command through a syn-
chronous 2-, 3- or 4-wire interface. This interface can be
Table 1. LTC2460/LTC2462 Output Data Format
SINGLE ENDED INPUT V
IN
(LTC2460)
DIFFERENTIAL INPUT VOLTAGE
V
IN
+
– V
IN
–
(LTC2462)
D15
(MSB)
D14 D13 D12...D2 D1 D0
(LSB)
CORRESPONDING
DECIMAL VALUE
≥V
REF
≥V
REF
1 1 1 1 1 1 65535
V
REF
– 1LSB V
REF
– 1LSB 1 1 1 1 1 0 65534
0.75 • V
REF
0.5 • V
REF
1 1 0 0 0 0 49152
0.75 • V
REF
– 1LSB 0.5 • V
REF
– 1LSB 1 0 1 1 1 1 49151
0.5 • V
REF
0 1 0 0 0 0 0 32768
0.5 • V
REF
– 1LSB –1LSB 0 1 1 1 1 1 32767
0.25 • V
REF
–0.5 • V
REF
0 1 0 0 0 0 16384
0.25 • V
REF
– 1LSB –0.5 • V
REF
– 1LSB 0 0 1 1 1 1 16383
0 ≤ –V
REF
0 0 0 0 0 0 0
LTC2460/LTC2462
11
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applicaTions inForMaTion
used during the CONVERT and SLEEP states to assess the
conversion status and during the DATA OUTPUT state to
read the conversion result, and to trigger a new conversion.
Serial Interface Operation Modes
The modes of operation can be summarized as follows:
1) The LTC2460/LTC2462 function with SCK idle high
(commonly known as CPOL = 1) or idle low (commonly
known as CPOL = 0).
2) After the 16th bit is read, a new conversion is started
if CS is pulled high or SCK is pulled low.
3) At any time during the Data Output state, pulling CS
high causes the part to leave the I/O state, abort the
output and begin a new conversion.
4) When SCK = HIGH, it is possible to monitor the conver-
sion status by pulling CS low and watching for SDO to
go low. This feature is available only in the idle-high
(CPOL = 1) mode.
Serial Clock Idle-High (CPOL = 1) Examples
In Figure 6, following a conversion cycle the LTC2460/
LTC2462 automatically enter the NAP mode with the ADC
powered down. The ADC’s reference will power down if the
SLP bit was set high prior to the just completed conversion
and CS is HIGH. Once CS goes low, the device powers up.
The user can monitor the conversion status at convenient
intervals using CS and SDO.
Pulling CS LOW while SCK is HIGH tests whether
or not the chip is in the CONVERT state. While in
the CONVERT state, SDO is HIGH while CS is LOW.
Once the conversion is complete, SDO is LOW
Figure 5. Conversion Status Monitoring Mode
NAP
t
1
t
2
SDO
SCK = HIGH
SDI = LOW
CONVERT
24602 F05
CS
Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.
The Rising Edge of CS Starts a New Conversion
D
15
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
D
14
D
13
D
12
D
2
D
1
D
0
SD0
SCK
CONVERT CONVERTNAP DATA OUTPUT
24602 F06
CS
SDI
EN2 SPD SLP
EN1
LTC2460/LTC2462
12
24602fa
while CS is LOW. These tests are not required op-
erational steps but may be useful for some applications.
When the data is available, the user applies 16 clock cycles
to transfer the result. The CS rising edge is then used to
initiate a new conversion.
The operation example of Figure 7 is identical to that of
Figure 6, except the new conversion cycle is triggered by
the falling edge of the serial clock (SCK).
Serial Clock Idle-Low (CPOL = 0) Examples
In Figure 8, following a conversion cycle the LTC2460/
LTC2462 automatically enters the NAP state. The device
reference will power down if the SLP bit was set high
prior to the just completed conversion and CS is HIGH.
Once CS goes low, the reference powers up. The user
determines data availability (and the end of conversion)
based upon external timing. The user then pulls CS low
(CS = ↓) and uses 16 clock cycles to transfer the result.
Following the 16th rising edge of the clock, CS is pulled high
(CS = ↑), which triggers a new conversion.
The timing diagram in Figure 9 is identical to that of Figure 8,
except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
and the CS signal is subsequently pulled high.
Examples of Aborting Cycle using CS
For some applications, the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2460/LTC2462
are in the data output state, a CS rising edge clears the
remaining data bits from the output register, aborts the out-
put cycle and triggers a new conversion. Figure 10 shows
an example of aborting an I/O with idle-high (CPOL = 1)
and Figure 11 shows an example of aborting an I/O with
idle-low (CPOL = 0).
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 12. If SCK is maintained at a low logic
level, after the end of a conversion cycle, a new conver-
sion operation can be triggered by pulling CS low and
then high. When CS is pulled low (CS = LOW), SDO will
applicaTions inForMaTion
Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
D
15
D
14
D
13
D
12
D
2
D
1
D
0
clk
1
clk
2
clk
3
clk
4
clk
14
clk
15
clk
16
SCK
SD0
CONVERT CONVERTNAP DATA OUTPUT
24602 F08
CS
SDI
EN2 SPD SLP
EN1
Figure 7. Idle-High (CPOL = 1) Clock Operation Example.
A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
clk
17
SCK
CONVERT CONVERTNAP DATA OUTPUT
24602 F07
CS
SDI
EN2 SPD SLP
EN1
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LTC2462IMS#TRPBF

Mfr. #:
Buy LTC2462IMS#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit SPI 60Hz Differential Delta Sigma ADC with Internal Reference
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