FM16W08
Document Number: 001-86210 Rev. *F Page 7 of 18
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on V
DD
relative to V
SS
........–1.0 V to + 7.0 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to V
DD
+ 0.5 V
Input voltage .......... –1.0 V to + 7.0 V and V
IN
< V
DD
+ 1.0 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to V
CC
+ 2.0 V
Package power dissipation
capability (T
A
= 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
Human Body Model (AEC-Q100-002 Rev. E) ............ 4 kV
Charged Device Model (AEC-Q100-011 Rev. B) .. 1.25 kV
Machine Model (AEC-Q100-003 Rev. E) ................. 300 V
Latch-up current ................................................... > 140 mA
Operating Range
Range Ambient Temperature (T
A
) V
DD
Industrial –40 C to +85 C 2.7 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ
[1]
Max Unit
V
DD
Power supply voltage 2.7 3.3 5.5 V
I
DD
V
DD
supply current V
DD
= 5.5 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or V
DD
– 0.2 V), all DQ pins unloaded.
––12mA
I
SB
Standby current V
DD
= 5.5 V, CE at V
IH
, All other pins are static
and at CMOS levels (0.2 V or V
DD
– 0.2 V)
–2050µA
I
LI
Input leakage current V
IN
between V
DD
and V
SS
––+A
I
LO
Output leakage current V
OUT
between V
DD
and V
SS
––+A
V
IH
Input HIGH voltage 0.7 × V
DD
–V
DD
+ 0.3 V
V
IL
Input LOW voltage – 0.3 0.3 × V
DD
V
V
OH1
Output HIGH voltage I
OH
= –1.0 mA, V
DD
> 2.7 V 2.4 V
V
OH2
Output HIGH voltage I
OH
= –100 µA V
DD
– 0.2 V
V
OL1
Output LOW voltage I
OL
= 2 mA, V
DD
> 2.7 V 0.4 V
V
OL2
Output LOW voltage I
OL
= 150 µA 0.2 V
Data Retention and Endurance
Parameter Description Test condition Min Max Unit
T
DR
Data retention At +85 C 10 Years
At +75 C38
At +65 C151
NV
C
Endurance Over operating temperature 10
14
Cycles
Note
1. Typical values are at 25 °C, V
DD
= V
DD
(typ). Not 100% tested.
FM16W08
Document Number: 001-86210 Rev. *F Page 8 of 18
AC Test Conditions
Input pulse levels .................................10% and 90% of V
DD
Input rise and fall times (10%–90%) ........................... < 5 ns
Input and output timing reference levels ...................0.5 V
DD
Output load capacitance............................................. 100 pF
Capacitance
Parameter
Description Test Conditions Max Unit
C
I/O
Input/Output capacitance (DQ) T
A
= 25 C, f = 1 MHz, V
DD
= V
DD
(Typ) 8 pF
C
IN
Input capacitance 6pF
Thermal Resistance
Parameter
Description Test Conditions 28-pin SOIC Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, in accordance with EIA/JESD51.
58 C/W
JC
Thermal resistance
(junction to case)
26 C/W
Figure 5. AC Test Loads
5.5 V
OUTPUT
C
L
R1
R2
497
919
100 pF
FM16W08
Document Number: 001-86210 Rev. *F Page 9 of 18
AC Switching Characteristics
Over the Operating Range
Parameters
[2]
Description
V
DD
= 2.7 V to 3.0 V V
DD
= 3.0 V to 5.5 V
Unit
Cypress
Parameter
Alt Parameter Min Max Min Max
SRAM Read Cycle
t
CE
t
ACE
Chip enable access time 80 70 ns
t
CA
Chip enable active time 80 70 ns
t
RC
Read cycle time 145 130 ns
t
PC
Pre-charge time 65 60 ns
t
AS
t
SA
Address setup time 0–0–ns
t
AH
t
HA
Address hold time 15 15 ns
t
OE
t
DOE
Output enable access time 15 12 ns
t
HZ
[3, 4]
t
HZCE
Chip Enable to output HI-Z 15 15 ns
t
OHZ
[3, 4]
t
HZOE
Output enable HIGH to output HI-Z 15 15 ns
Notes
2. Test conditions assume a signal transition time of 5 ns or less, timing reference levels of 0.5 × V
DD
, input pulse levels of 10% and 90% of V
DD
, output loading of the
specified I
OL
/I
OH
and load capacitance shown in AC Test Conditions on page 8.
3. t
HZ
and t
OHZ
are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
4. This parameter is characterized but not 100% tested.

FM16W08-SGTR

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
F-RAM 64Kb 70ns 8K x 8 Parallel FRAM
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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