Data Sheet ADV7280
Rev. A | Page 11 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
24
INTRQ
23
A
IN
4
22
A
IN
3
21
A
VDD
20
VREFN
19
VREFP
18
A
IN
2
17
A
IN
1
1
2
3
4
5
6
7
8
DGND
D
VDDIO
D
VDD
DGND
P7
P6
P5
P4
9
10
11
12
13
14
15
16
P3
P2
P1
P0
D
VDD
XTALP
XTALN
P
VDD
32
31
30
29
28
27
26
25
LLC
PWRDWN
HS
VS/FIELD/SFL
SCLK
SDATA
ALSB
RESET
ADV7280
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
11634-006
Figure 6. Pin Configuration, ADV7280
Table 9. Pin Function Descriptions, ADV7280
Pin No. Mnemonic Type Description
Ground for Digital Supply.
2 D
VDDIO
Power Digital I/O Power Supply (1.8 V or 3.3 V).
3, 13 D
VDD
Power Digital Power Supply (1.8 V).
5 to 12 P7 to P0 Output Video Pixel Output Ports.
14 XTALP Output
Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external
1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280. The crystal used
with the ADV7280 must be a fundamental crystal.
15 XTALN Input
Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7280 must
be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used
to clock the ADV7280, the output of the oscillator is fed into the XTALN pin.
16 P
VDD
Power PLL Power Supply (1.8 V).
17, 18,
22, 23
IN
IN
Analog Video Input Channels.
19 VREFP Output Internal Voltage Reference Output.
20 VREFN Output Internal Voltage Reference Output.
21 A
VDD
Power Analog Power Supply (1.8 V).
24
INTRQ
Output
Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
25
RESET
Input
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7280 circuitry.
26 ALSB Input
This pin selects the I
2
C write address for the ADV7280. When ALSB is set to Logic 0, the write
address is 0x40; when ALSB is set to Logic 1, the write address is 0x42.
I
2
C Port Serial Data Input/Output.
28 SCLK Input I
2
C Port Serial Clock Input. The maximum clock rate is 400 kHz.
29 VS/FIELD/SFL Output
Vertical Synchronization Output Signal/Field Synchronization Output Signal/Subcarrier
Frequency Lock. When configured for the SFL function, this pin provides a serial output
stream that can be used to lock the subcarrier frequency when the ADV7280 decoder is
connected to any Analog Devices, Inc., digital video encoder.
Horizontal Synchronization Output Signal.
31
PWRDWN
Input Power-Down Pin. A logic low on this pin places the ADV7280 in power-down mode.
32 LLC Output
Line-Locked Output Clock for Output Pixel Data. The clock output is nominally 27 MHz, but
it increases or decreases according to the video line length.
EPAD (EP) Exposed Pad. The exposed pad must be connected to DGND.