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ADV7280WBCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
ADV7280 Data Sheet
Rev. A | Page 12 of 28
ADV7280-M
TOP VIEW
(Not to Scale)
24
A
IN
5
23
A
IN
4
22
A
IN
3
21
A
VDD
20
VREFN
19
VREFP
18
A
IN
2
17
A
IN
1
1
2
3
4
5
6
7
8
DGND
D
VDDIO
D
VDD
DGND
INTRQ
GPO2
GPO1
GPO0
9
10
11
12
13
14
15
16
D0P
D0N
CLKP
CLKN
M
VDD
XTALP
XTALN
P
VDD
32
31
30
29
28
27
26
25
PWRDWN
SCLK
SDATA
ALSB
RESET
A
IN
8
A
IN
7
A
IN
6
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
11634-007
Figure 7. Pin Configuration, ADV7280-M
Table 10. Pin Function Descriptions, ADV7280-M
Pin No. Mnemonic Type Description
1, 4 DGND Ground Ground for Digital Supply.
2 D
VDDIO
Power Digital I/O Power Supply (3.3 V).
3 D
VDD
Power Digital Power Supply (1.8 V).
5
INTRQ
Output
Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
6 to 8
GPO2 to
GPO0
Output
General-Purpose Outputs. These pins can be configured via I
2
C to allow control of external
devices.
9 D0P Output Positive MIPI Differential Data Output.
10 D0N Output Negative MIPI Differential Data Output.
11 CLKP Output Positive MIPI Differential Clock Output.
12 CLKN Output Negative MIPI Differential Clock Output.
13
M
VDD
Power
MIPI Digital Power Supply (1.8 V).
14 XTALP Output
Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external
1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280-M. The crystal used
with the ADV7280-M must be a fundamental crystal.
15 XTALN Input
Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7280-M must
be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to
clock the ADV7280-M, the output of the oscillator is fed into the XTALN pin.
16 P
VDD
Power PLL Power Supply (1.8 V).
17, 18, 22,
23, 24, 25,
26, 27
A
IN
1 to A
IN
8 Input Analog Video Input Channels.
19
VREFP
Output
Internal Voltage Reference Output.
20 VREFN Output Internal Voltage Reference Output.
21 A
VDD
Power Analog Power Supply (1.8 V).
28
RESET
Input
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7280-M circuitry.
29 ALSB Input
This pin selects the I
2
C write address for the ADV7280-M. When ALSB is set to Logic 0, the
write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42.
30 SDATA Input/output I
2
C Port Serial Data Input/Output.
31 SCLK Input I
2
C Port Serial Clock Input. The maximum clock rate is 400 kHz.
32
PWRDWN
Input Power-Down Pin. A logic low on this pin places the ADV7280-M in power-down mode.
EPAD (EP) Exposed Pad. The exposed pad must be connected to DGND.
Data Sheet ADV7280
Rev. A | Page 13 of 28
THEORY OF OPERATION
The ADV7280/ADV7280-M are versatile one-chip, multiformat
video decoders. The ADV7280/ADV7280-M automatically detect
standard analog baseband video signals compatible with world-
wide NTSC, PAL, and SECAM standards in the form of composite,
S-Video, and component video.
The ADV7280 converts the analog video signals into an 8-bit
YCrCb 4:2:2 component video data stream that is compatible
with the ITU-R BT.656 interface standard.
The ADV7280-M converts the analog video signals into an 8-bit
YCrCb 4:2:2 video data stream that is output over a MIPI CSI-2
interface. The MIPI CSI-2 output interface connects to a wide
range of video processors and FPGAs.
The ADV7280/ADV7280-M accept composite video signals,
as well as S-Video and YPbPr video signals, supporting a wide
range of consumer and automotive video sources. The accurate
10-bit analog-to-digital conversion provides professional quality
video performance for consumer applications with true 8-bit
data resolution.
The advanced interlaced-to-progressive (I2P) function allows the
ADV7280/ADV7280-M to convert an interlaced video input into
a progressive video output. This function is performed without the
need for external memory. The ADV7280/ADV7280-M use edge
adaptive technology to minimize video defects on low angle lines.
The automatic gain control (AGC) and clamp restore circuitry
allows an input video signal peak-to-peak range of 0 V to 1.0 V
at the analog video input pins of the ADV7280/ADV7280-M.
Alternatively, the AGC and clamp restore circuitry can be bypassed
for manual settings.
The ADV7280/ADV7280-M support a number of other func-
tions, including 8-bit to 6-bit down dither mode and adaptive
contrast enhancement (ACE).
The ADV7280/ADV7280-M are programmed via a 2-wire,
serial bidirectional port (I
2
C compatible) and are fabricated in
a 1.8 V CMOS process. The monolithic CMOS construction
of the ADV7280/ADV7280-M ensures greater functionality with
lower power dissipation. The LFCSP package option makes these
decoders ideal for space-constrained portable applications.
ANALOG FRONT END (AFE)
The analog front end (AFE) of the ADV7280/ADV7280-M
comprises a single high speed, 10-bit ADC that digitizes the
analog video signal before applying it to the standard definition
processor (SDP).
The AFE also includes an input mux that enables multiple video
signals to be applied to the
ADV7280/ADV7280-M. The input
mux allows up to four composite video signals to be applied to
the ADV7280 and up to eight composite video signals to be applied
to the ADV7280-M.
Current clamps are positioned in front of the ADC to ensure
that the video signal remains within the range of the converter.
A resistor divider network is required before each analog input
channel to ensure that the input signal is kept within the range of
the ADC (see the Input Network section). Fine clamping of the
video signal is performed downstream by digital fine clamping
within the ADV7280/ADV7280-M.
Table 11 lists the three ADC clock rates that are determined by
the video input format to be processed. These clock rates ensure
4× oversampling per channel for CVBS, Y/C, and YPrPb modes.
Table 11. ADC Clock Rates
Input Format ADC Clock Rate (MHz)
1
Oversampling
Rate per Channel
CVBS 57.27 4×
Y/C (S-Video) 114 4×
YPrPb 172 4×
1
Based on a 28.63636 MHz crystal between the XTALP and XTALN pins.
ADV7280 Data Sheet
Rev. A | Page 14 of 28
STANDARD DEFINITION PROCESSOR (SDP)
The ADV7280/ADV7280-M are capable of decoding a large
selection of baseband video signals in composite, S-Video, and
component formats. The video standards supported by the
video processor include
• PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N,
PAL Nc, PAL 60
• NTSC J, NTSC M, NTSC 4.43
• SECAM B, SECAM D, SECAM G, SECAM K, SECAM L
Using the standard definition processor (SDP), the ADV7280/
ADV7280-M can automatically detect the video standard and
process it accordingly.
The ADV7280/ADV7280-M have a five-line adaptive 2D
comb filter that provides superior chrominance and luminance
separation when decoding a composite video signal. This highly
adaptive filter automatically adjusts its processing mode according
to the video standard and signal quality without user intervention.
Video user controls such as brightness, contrast, saturation, and
hue are also available with the ADV7280/ADV7280-M.
The ADV7280/ADV7280-M implement the patented Adaptive
Digital Line Length Tracking (ADLLT™) algorithm to track vary-
ing video line lengths from sources such as VCRs. ADLLT enables
the ADV7280/ADV7280-M to track and decode poor quality
video sources such as VCRs and noisy sources from tuner outputs
and camcorders. The ADV7280/ADV7280-M contain a chroma
transient improvement (CTI) processor that sharpens the edge
rate of chroma transitions, resulting in sharper vertical transitions.
Adaptive contrast enhancement (ACE) offers improved visual
detail using an algorithm that automatically varies contrast levels
to enhance picture detail. ACE increases the contrast in dark areas
of an image without saturating the bright areas of the image. This
feature is particularly useful in automotive applications, where
it can be important to discern objects in shaded areas.
Down dithering converts the output of the ADV7280/ADV7280-M
from an 8-bit to a 6-bit output, enabling ease of design for standard
LCD panels.
The I2P block converts the interlaced video input into a progressive
video output without the need for external memory.
The SDP can process a variety of VBI data services, such as closed
captioning (CCAP), wide screen signaling (WSS), and copy gen-
eration management system (CGMS). VBI data is transmitted
as ancillary data packets.
The ADV7280/ADV7280-M are fully Rovi® (Macrovision®)
compliant; detection circuitry enables Type I, Type II, and Type III
protection levels to be identified and reported to the user. The
decoders are also fully robust to all Macrovision signal inputs.
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ADV7280WBCPZ

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Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10-bit SD Video Decoder
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