8516FYLFT Datasheet 8516FYLF, 8516FYLFT, 8516FY | P10-P12

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

8516 DATA SHEET

10 REVISION B 6/11/15

FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

3.3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

125

Zo = 50 Ohm

3.3V

125

LVPECL

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both V

SWING

and V

must meet the

and V

CMR

input requirements. Figures 2A to 2E show inter-

face examples for the HiPerClockS CLK/nCLK input driven by

the most common driver types. The input interfaces suggested

FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

ICS HIPERCLOCKS LVHSTL DRIVER

here are examples only. Please consult with the vendor of the

driver component to conﬁ rm the driver termination requirements.

For example in Figure 2A, the input termination applies for ICS

HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

1.8V

Input

LVHSTL Driver

ICS

HiPerClockS

LVHSTL

3.3V

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER WITH AC COUPLE

Zo = 50 Ohm

125

HiPerClockS

CLK

nCLK

3.3V

100 - 200

3.3V

100 - 200

Input

R5,R6 locate near the driver pin.

Zo = 50 Ohm

125

LVPECL

Zo = 50 Ohm

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

REVISION B 6/11/15

8516 DATA SHEET

11 LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 3. In a 100Ω

differential transmission line environment, LVDS drivers require

a matched load termination of 100Ω across near the receiver

input. For a multiple LVDS outputs buffer, if only partial outputs

are used, it is recommended to terminate the un-used outputs.

FIGURE 3. TYPICAL LVDS DRIVER TERMINATION

3.3V

100

Zo = 50 Ohm

LVDS_Driver

HiPerClockS

CLK

nCLK

Zo = 50 Ohm

3.3V

FIGURE 4. ICS8516 LVDS BUFFER SCHEMATIC EXAMPLE

0.1u

(U1-12)

Zo = 50 Ohm

(U1-25)

LVDS_input

(U1-31)

Zo = 50 Ohm

0.1u

8516

VDD

nQ5

nQ4

VDD

GND

nQ3

nQ2

VDD

nQ1

nQ0

GND

nCLK

CLK

GND

Q15

nQ15

Q14

nQ14

VDD

nQ10

Q10

nQ11

Q11

VDD

GND

nQ12

Q12

nQ13

Q13

VDD

nQ6

nQ7

GND

OE1

OE2

GND

nQ8

nQ9

Zo = 50 Ohm

R16

100

Zo = 50 Ohm

VDD=3.3V

LVDS_input

Zo = 50 Ohm

VDD=3.3V

R10

100

0.1u

LVDS_Driver

R17

100

LVDS_input

(U1-1)

Decoupling capacitors located near the power pins

(U1-6) (U1-36)

100

0.1u

SCHEMATIC EXAMPLE

Figure 4 shows a schematic example of ICS8516. In this

example, the input is driven by an LVDS driver. For LVDS buffer,

it is recommended to terminate the unused outputs for better

signal integrity. The decoupling capacitors should be physically

located near the power pin.

LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

8516 DATA SHEET

12 REVISION B 6/11/15

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS8516 is: 1821

TABLE 6. θ

VS. AIR FLOW TABLE FOR 48 LEAD LQFP

by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

8516FYLFT

Mfr. #:

Buy 8516FYLFT

Manufacturer:

IDT

Description:

Clock Drivers & Distribution 1-to-16 LVDS Fanout Buffer

Lifecycle:

New from this manufacturer.

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8516FYLFT

8516FYLFT

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