CY7C421
Document Number: 38-06001 Rev. *K Page 7 of 22
Capacitance
Parameter
[5]
Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25 °C, f = 1 MHz, V
CC
= 4.5 V 6 pF
C
OUT
Output Capacitance 6 pF
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.0 V
5 V
OUTPUT
R1 500
Ω
R2
333Ω
30 pF
INCLUDING
JIGAND
SCOPE
GND
90%
10%
90%
10%
3ns
3
ns
5 V
OUTPUT
R1 500 Ω
R2
333Ω
5pF
INCLUDING
JIGAND
SCOPE
OUTPUT 2 V
Equivalent to: THÉ VENIN EQUIVALENT
(b)(a)
ALL INPUT PULSES
200Ω
Note
5. Tested initially and after any design or process changes that may affect these parameters.
CY7C421
Document Number: 38-06001 Rev. *K Page 8 of 22
Switching Characteristics
Over the Operating Range
Parameter
[6]
Description
-15 -20
Unit
Min Max Min Max
t
RC
Read Cycle Time 25 30 ns
t
A
Access Time 15 20 ns
t
RR
Read Recovery Time 10 10 ns
t
PR
Read Pulse Width 15 20 ns
t
LZR
[7]
Read LOW to Low Z 3 3 ns
t
DVR
[7, 8]
Data Valid after Read HIGH 5 5 ns
t
HZR
[7, 8]
Read HIGH to High Z 15 15 ns
t
WC
Write Cycle Time 25 30 ns
t
PW
Write Pulse Width 15 20 ns
t
HWZ
[7]
Write HIGH to Low Z 5 5 ns
t
WR
Write Recovery Time 10 10 ns
t
SD
Data Setup Time 8 12 ns
t
HD
Data Hold Time 0 0 ns
t
MRSC
MR Cycle Time 25 30 ns
t
PMR
MR Pulse Width 15 20 ns
t
RMR
MR Recovery Time 10 10 ns
t
RPW
Read HIGH to MR HIGH 15 20 ns
t
WPW
Write HIGH to MR HIGH 15 20 ns
t
RTC
Retransmit Cycle Time 25 30 ns
t
PRT
Retransmit Pulse Width 15 20 ns
t
RTR
Retransmit Recovery Time 10 10 ns
t
EFL
MR to EF LOW 25 30 ns
t
HFH
MR to HF HIGH 25 30 ns
t
FFH
MR to FF HIGH 25 30 ns
t
REF
Read LOW to EF LOW 15 20 ns
t
RFF
Read HIGH to FF HIGH 15 20 ns
t
WEF
Write HIGH to EF HIGH 15 20 ns
t
WFF
Write LOW to FF LOW 15 20 ns
t
WHF
Write LOW to HF LOW 15 20 ns
t
RHF
Read HIGH to HF HIGH 15 20 ns
t
RAE
Effective Read from Write HIGH 15 20 ns
t
RPE
Effective Read Pulse Width after EF HIGH 15 20 ns
t
WAF
Effective Write from Read HIGH 15 20 ns
t
WPF
Effective Write Pulse Width after FF HIGH 15 20 ns
t
XOL
Expansion Out LOW Delay from Clock 15 20 ns
t
XOH
Expansion Out HIGH Delay from Clock 15 20 ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V and output loading of the specified I
OL
/I
OH
and 30 pF load capacitance,
as in part (a) of Figure 4 on page 7, unless otherwise specified.
7. t
HZR
transition is measured at +200 mV from V
OL
and –200 mV from V
OH
. t
DVR
transition is measured at the 1.5V level. t
HWZ
and t
LZR
transition is measured at
±100 mV from the steady state.
8. t
HZR
and t
DVR
use capacitance loading as in part (b) of Figure 4 on page 7.
CY7C421
Document Number: 38-06001 Rev. *K Page 9 of 22
Switching Waveforms
Figure 5. Asynchronous Read and Write
Figure 6. Master Reset
Figure 7. Half-full Flag
DATA VALIDDATA VALID
DATA VALID DATA VALID
t
SD
t
HD
t
RC
t
PR
t
A
t
RR
t
A
t
LZR
t
DVR
t
HZR
t
WC
t
PW
t
WR
R
Q
0
–Q
8
W
D
0
–D
8
MR
R,W
HF
FF
EF
t
MRSC
t
PMR
t
EFL
t
HFH
t
FFH
t
RPW
t
WPW
t
RMR
[9]
[10]
HALF FULL+1HALF FULL HALF FULL
W
R
HF
t
WHF
t
RHF

CY7C421-20JXC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
FIFO 512x9 .300" PARALLEL CASCADEABLE FIFO COM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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