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2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 10 of 12
IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (PART2 OF 2)
(Values are for the DDR4 SDRAM only and are computed from values specified in the vendor’s component data sheet)
Symbol Proposed Conditions Value Units
IDD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between WR;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different
data between one burst and the next one ; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at HIGH; Pattern Details: Refer to
Component Datasheet for detail pattern
2,810
mA
IDD5B
Burst Refresh Current (1X REF)
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High
between REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at
1; Bank Activity: REF command every nRFC ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern
Details: Refer to Component Datasheet for detail pattern
5,040
mA
IPP5B
Burst Refresh Write IPP Current (1X REF)
Same condition with IDD5B
378
mA
IDD6N
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL:
Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address,
Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT
Signal: MID-LEVEL
860
mA
IDD6E
Self-Refresh Current: Extended Temperature Range)
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock: Off; CK_t and CK_c: LOW; CL:
Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address,
Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: MID-LEVEL
1,250
mA
IDD6R
Self-Refresh Current: Reduced Temperature Range
TCASE: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low; External clock: Off; CK_t and CK_c#:
LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank
Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT:
Enabled in Mode Registers2; ODT Signal: MID-LEVEL
610
mA
IDD6A
Auto Self-Refresh Current
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4;Partial Array Self-Refresh (PASR): Full Array; CKE: Low;
External clock: Off; CK_t and CK_c#: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command,
Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh operation; Output
Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
820
mA
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern; BL:
81; AL: CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially
toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM_n: stable at 1; Bank Activity: two
times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers2;
ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
5,460
mA
IPP7
Operating Bank Interleave Read IPP Current
Same condition with IDD7
207
mA
IDD8
Maximum Power Down Current
430
mA
PDIMM
Power Consumption per DIMM
System is operating at 1200MHz clock with VDD = 1.2V. This parameter is calculated at a common loading.
6,560
mW