10
LT1182/LT1183/LT1184/LT1184F
LT1182/LT1183/LT1184/LT1184F
CCFL PGND (Pin 1): This pin is the emitter of an internal
NPN power switch. CCFL switch current flows through
this pin and permits internal, switch-current sensing. The
regulators provide a separate analog ground and power
ground(s) to isolate high current ground paths from low
current signal paths. Linear Technology recommends the
use of star-ground layout techniques.
I
CCFL
(Pin 2): This pin is the input to the CCFL lamp current
programming circuit. This pin internally regulates to 450mV
(LT1182/LT1183) or 465mV (LT1184/LT1184F). The pin
accepts a DC input current signal of 0µA to 100µA full
scale. This input signal is converted to a 0µA to 500µA
source current at the CCFL V
C
pin. By shunt regulating the
I
CCFL
pin, the input programming current can be set with
DAC, PWM or potentiometer control. As input program-
ming current increases, the regulated lamp current in-
creases. For a typical 6mA lamp, the range of input
programming current is about 0µA to 50µA.
DIO (Pin 3): This pin is the common connection between
the cathode and anode of two internal diodes. The remain-
ing terminals of the two diodes connect to ground. In a
grounded lamp configuration, DIO connects to the low
voltage side of the lamp. Bidirectional lamp current flows
in the DIO pin and thus the diodes conduct alternately on
half cycles. Lamp current is controlled by monitoring one-
half of the average lamp current. The diode conducting on
negative half cycles has one-tenth of its current diverted to
the CCFL V
C
pin. This current nulls against the source
current provided by the lamp-current programmer circuit.
A single capacitor on the CCFL V
C
pin provides both stable
loop compensation and an averaging function to the half-
wave-rectified sinusoidal lamp current. Therefore, input
programming current relates to one-half of average lamp
current. This scheme reduces the number of loop com-
pensation components and permits faster loop transient
response in comparison to previously published circuits.
If a floating-lamp configuration is used, ground the DIO
pin.
CCFL V
C
(Pin 4): This pin is the output of the lamp current
programmer circuit and the input of the current compara-
tor for the CCFL regulator. Its uses include frequency
compensation, lamp-current averaging for grounded lamp
circuits, and current limiting. The voltage on the CCFL V
C
pin determines the current trip level for switch turnoff.
During normal operation this pin sits at a voltage between
0.95V (zero switch current) and 2.0V (maximum switch
current) with respect to analog ground (AGND). This pin
has a high impedance output and permits external voltage
clamping to adjust current limit. A single capacitor to
ground provides stable loop compensation. This simpli-
fied loop compensation method permits the CCFL regula-
tor to exhibit single-pole transient response behavior and
virtually eliminates transformer output overshoot.
AGND (Pin 5): This pin is the low current analog ground.
It is the negative sense terminal for the internal 1.24V
reference and the I
CCFL
summing voltage in the LT1182/
LT1183/LT1184/LT1184F. It is also a sense terminal for
the LCD dual input error amplifier in the LT1182/LT1183.
Connect external feedback divider networks that terminate
to ground and frequency compensation components that
terminate to ground directly to this pin for best regulation
and performance.
SHUTDOWN (Pin 6): Pulling this pin low causes complete
regulator shutdown with quiescent current typically re-
duced to 35µA. The nominal threshold voltage for this pin
is 0.85V. If the pin is not used, it can float high or be pulled
to a logic high level (maximum of 6V). Carefully evaluate
active operation when allowing the pin to float high.
Capacitive coupling into the pin from switching transients
could cause erratic operation.
CCFL V
SW
(Pin 16): This pin is the collector of the internal
NPN power switch for the CCFL regulator. The power
switch provides a minimum of 1.25A. Maximum switch
current is a function of duty cycle as internal slope com-
pensation ensures stability with duty cycles greater than
50%. Using a driver loop to automatically adapt base drive
current to the minimum required to keep the switch in a
quasi-saturation state yields fast switching times and high
efficiency operation. The ratio of switch current to driver
current is about 50:1.
PIN FUNCTIONS
UUU
11
LT1182/LT1183/LT1184/LT1184F
Bulb (Pin 15): This pin connects to the low side of a 7V
threshold comparator between the BAT and Bulb pins.
This circuit sets the maximum voltage level across the
primary side of the Royer converter under all operating
conditions and limits the maximum secondary output
under start-up conditions or open lamp conditions. This
eases transformer voltage rating requirements. Set the
voltage limit to insure lamp start-up with worst-case, lamp
start voltages and cold-temperature system operating
conditions. The Bulb pin connects to the junction of an
external divider network. The divider network connects
from the center tap of the Royer transformer or the actual
battery supply voltage to the top side of the current source
“tail inductor”. A capacitor across the top of the divider
network filters switching ripple and sets a time constant
that determines how quickly the clamp activates. When
the comparator activates, sink current is generated to pull
the CCFL V
C
pin down. This action transfers the entire
regulator loop from current mode operation into voltage
mode operation.
BAT (Pin 14): This pin connects to the battery or battery
charger voltage from which the CCFL Royer converter and
LCD contrast converter operate. This voltage is typically
higher than the V
IN
supply voltage but can be equal or less
than V
IN
. However, the BAT voltage must be at least 2.1V
greater than the internal 2.4V regulator or 4.5V minimum
up to 30V maximum. This pin provides biasing for the
lamp current programming block, is used with the Royer
pin for floating lamp configurations, and connects to one
input for the open lamp protection circuitry. For floating
lamp configurations, this pin is the noninverting terminal
of a high-side current sense amplifier. The typical quies-
cent current is 50µA into the pin. The BAT and Royer pins
monitor the primary side Royer converter current through
an internal 0.1 top side current sense resistor. A 0A to 1A
primary side, center tap converter current is translated to
an input signal range of 0mV to 100mV for the current
sense amplifier. This input range translates to a 0µA to
500µA sink current at the CCFL V
C
pin that nulls against the
source current provided by the programmer circuit. The
BAT pin also connects to the top side of an internal clamp
between the BAT and Bulb pins.
PIN FUNCTIONS
UUU
Royer (Pin 13): This pin connects to the center-tapped
primary of the Royer converter and is used with the BAT
pin in a floating lamp configuration where lamp current is
controlled by sensing Royer primary side converter cur-
rent. This pin is the inverting terminal of a high-side
current sense amplifier. The typical quiescent current is
50µA into the pin. If the CCFL regulator is not used in a
floating lamp configuration, tie the Royer and BAT pins
together. This pin is only available on the LT1182/LT1183/
LT1184F.
V
IN
(Pin 12): This pin is the supply pin for the LT1182/
LT1183/LT1184/LT1184F. The ICs accept an input voltage
range of 3V minimum to 30V maximum with little change
in quiescent current (zero switch current). An internal,
low dropout regulator provides a 2.4V supply for most of
the internal circuitry. Supply current increases as switch
current increases at a rate approximately 1/50 of switch
current. This corresponds to a forced Beta of 50 for each
switch. The ICs incorporate undervoltage lockout by sens-
ing regulator dropout and lockout switching for input
voltages below 2.5V. Hysteresis is not used to maximize
the useful range of input voltage. The typical input voltage
is a 3.3V or 5V logic supply.
LT1182/LT1183
LCD V
C
(Pin 7): This pin is the output of the LCD contrast
error amplifier and the input of the current comparator for
the LCD contrast regulator. Its uses include frequency
compensation and current limiting. The voltage on the
LCD V
C
pin determines the current trip level for switch
turnoff. During normal operation, this pin sits at a voltage
between 0.95V (zero switch current) and 2.0V (maximum
switch current). The LCD V
C
pin has a high impedance
output and permits external voltage clamping to adjust
current limit. A series R/C network to ground provides
stable loop compensation.
LCD PGND (Pin 8): This pin is the emitter of an internal
NPN power switch. LCD contrast switch current flows
through this pin and permits internal, switch-current
sensing. The regulators provide a separate analog ground
and power ground(s) to isolate high current ground paths
from low current signal paths. Linear Technology recom-
mends star-ground layout techniques.
12
LT1182/LT1183/LT1184/LT1184F
PIN FUNCTIONS
UUU
LCD V
SW
(Pin 9): This pin is the collector of the internal
NPN power switch for the LCD contrast regulator. The
power switch provides a minimum of 625mA. Maximum
switch current is a function of duty cycle as internal slope
compensation ensures stability with duty cycles greater
than 50%. Using a driver loop to automatically adapt base
drive current to the minimum required to keep the switch
in a quasi-saturation state yields fast switching times and
high efficiency operation. The ratio of switch current to
driver current is about 50:1.
LT1182
FBN (Pin 10): This pin is the noninverting terminal for the
negative contrast control error amplifier. The inverting
terminal is offset from ground by –12mV and defines the
error amplifier output state under start-up conditions. The
FBN pin acts as a summing junction for a resistor divider
network. Input bias current for this pin is typically 1µA
flowing out of the pin. If this pin is not used, force FBN to
greater than 0.5V to deactivate the negative contrast
control input stage. The proximity of FBN to the LCD V
SW
pin makes it sensitive to ringing on the switch pin. A small
capacitor (0.01µF) from FBN to ground filters switching
ripple.
FBP (Pin 11): This pin is the inverting terminal for the
positive contrast control error amplifier. The noninverting
terminal is tied to an internal 1.244V reference. Input bias
current for this pin is typically 0.5µA flowing into the pin.
If this pin is not used, ground FBP to deactivate the positive
contrast control input stage. The proximity of FBP to the
LCD V
SW
pin makes it sensitive to ringing on the switch
pin. A small capacitor (0.01µF) from FBP to ground filters
switching ripple.
LT1183
FB (Pin 10): This pin is the common connection between
the noninverting terminal for the negative contrast error
amplifier and the inverting terminal for the positive-con-
trast error amplifier. In comparison to the LT1182, the FBN
and the FBP pins tie together and come out as one pin. This
scheme permits one polarity of contrast to be regulated.
The proximity of FB to the LCD V
SW
pin makes it sensitive
to ringing on the switch pin. A small capacitor (0.01µF)
from FB to ground filters switching ripple.
The FB pin requires attention to start-up conditions when
generating negative contrast voltages. The pin has two
stable operating points; regulating to 1.244V for positive
contrast voltages or regulating to –12mV for negative
contrast voltages. Under start-up conditions, the FB pin
heads to a positive voltage. If negative contrast voltages
are generated, tie a diode from the FB pin to ground. This
ensures that the FB pin will clamp before reaching the
positive reference voltage. Switching action then pulls the
FB pin back to its normal servo voltage.
LT1183/LT1184/LT1184F
REF (Pin 11): This pin brings out the 1.244V reference. Its
functions include the programming of negative contrast
voltages with an external resistor divider network (LT1183
only) and the programming of lamp current for the I
CCFL
pin. LTC does not recommend using the REF pin for both
functions at once. The REF pin has a typical output
impedance of 45 on the LT1183 and a typical output
impedance of 15 on the LT1184/LT1184F. Reference
load current should be limited to a few hundred microam-
peres, otherwise reference regulation will be degraded.
REF is used to generate the maximum programming
current for the I
CCFL
pin by placing a resistor between the
pins. PWM or DAC control subtracts from the maximum
programming current. A small decoupling capacitor (0.1uF)
is recommended to filter switching transients.

LT1182CS

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators LT1182 - CCFL/LCD Contrast Switching Regulators
Lifecycle:
New from this manufacturer.
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