NCN8026A
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13
MULTIPLE CARD OPERATION
The chip select (CS) feature of the NCN8026A allows the
microcontroller to communicate with multiple smart cards,
reducing the number of pins used on the microcontroller. For
this feature to work, all cards in the system must be present
and active at all times (CVCC enabled). When CVCC is
deactivated, low impedance active pull−up circuits are
enabled on I/Ouc, AUX1uc, and AUX2uc. If any of these
pins are shared in a multiple card system, the active pull up
circuit can prevent the pin from reaching low logic voltage
levels.
Enable CVCC on all cards by toggling CMDVCC
from
high to low on all devices. The CS
pin is used to enable and
disable communication with the smart card without
disabling CVCC. When the CS
pin is logic high, CMDVCC,
VSEL0, VSEL1, CLKDIV1, CLKDIV2, and RSTIN
become latched internally in the NCN8026A device. Use the
CS
pin to control communication between specific smart
cards.
If I/Ouc and AUXuc pins of multiple NCN8026A devices
are connected commonly to the microcontroller, each
NCN8026A’s CMDVCC
should be set low to avoid bus
collision on I/Ouc, AUX1uc, and AUX2uc. If disabling
CVCC on any cards not in use, add a disconnecting function
such as an analog switch on the I/Ouc, AUX1uc, and
AUX2uc pins on that device.
WHEN CARD IS NOT IN USE
When the NCN8026A is powered on, CVCC is off. Upon
power on, I/Ouc, AUX1uc, and AUX2uc pins are driven
high with a low impedance active pull−up circuit sourcing
about 25 mA. The microcontroller’s I/O pins should be set
to a high impedance or input state during this time.
When CMDVCC
is switched from high to low, CVCC
turns on. I/Ouc, AUX1uc, and AUX2uc are not driven by the
active pull−up circuit when CVCC is enabled and the
high−impedance pull−up resistor dominates.
When CMDVCC
is switched from low to high, CVCC
turns off. The I/Ouc, AUX1uc, and AUX2uc pins are driven
high again with a low impedance active pull−up circuit
sourcing about 25 mA. The microcontroller’s I/O pins
should be set to a high impedance or input state during this
time.
ESD PROTECTION
The NCN8026A includes devices to protect the pins
against the ESD spike voltages. To cope with the different
ESD voltages developed across these pins, the built in
structures have been designed to handle either 2 kV, when
related to the micro controller side, or 8 kV when connected
with the external contacts (HBM model). Practically, the
CRST, CCLK, CI/O, CAUX1, CAUX2, PRES and PRES
pins can sustain 8 kV. The CVCC pin has the same ESD
protection and can source up to 70 mA continuously, the
absolute maximum current being internally limited with a
max at 150 mA. The CVCC current limit depends on V
DDP
and CVCC.