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74VHCT541AFT

P1-P3P4-P6P7-P8
74VHCT540AFT,74VHCT541AFT
1
CMOS Digital Integrated Circuits Silicon Monolithic
74VHCT540AFT,74VHCT541AFT
74VHCT540AFT,74VHCT541AFT
74VHCT540AFT,74VHCT541AFT
74VHCT540AFT,74VHCT541AFT
Start of commercial production
2013-01
1.
1.
1.
1. Functional Description
Functional Description
Functional Description
Functional Description
• Octal Bus Buffer
74VHCT540AFT: INVERTED, 3-STATE OUTPUTS
74VHCT541AFT: NON-INVERTED, 3-STATE OUTPUTS
2.
2.
2.
2. General
General
General
General
The 74VHCT540AFT and 74VHCT541AFT are advanced high speed CMOS OCTAL BUS BUFFERs fabricated
with silicon gate C
2
MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining the CMOS low power dissipation.
The 74VHCT540AFT is an inverting type and, the 74VHCT541AFT is a non-inverting type.
When either G1 or G2 are high, the terminal outputs are in the high-impedance state.
The input voltage are compatible with TTL output voltage.
These devices may be used as a level converter for interfacing 3.3 V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins
without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and
input/output voltages such as battery back up, hot board insertion, etc.
Note: Output in off-state
3.
3.
3.
3. Features
Features
Features
Features
(1) AEC-Q100 (Rev. H) (Note 1)
(2) Wide operating temperature range: T
opr
= -40 to 125
(3) High speed: Propagation delay time = 5.4 ns (typ.) at V
CC
= 5.0 V
(4) Quiescent supply current: I
CC
= 4.0 µA (max) at T
a
= 25
(5) Compatible with TTL input: V
IL
= 0.8 V (max)
V
IH
= 2.0 V (min)
(6) Power down protection is provided on all inputs and outputs.
(7) Balanced propagation delays: t
PLH
≈ t
PHL
(8) Low noise: V
OLP
= 1.5 V (max)
(9) Pin and function compatible with the 74 series
(ACT/HCT/AHCT etc.) 540/541 type.
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
2017-02-23
Rev.4.0
©2017 Toshiba Corporation
74VHCT540AFT,74VHCT541AFT
2
4.
4.
4.
4. Packaging
Packaging
Packaging
Packaging
TSSOP20B
5.
5.
5.
5. Pin Assignment
Pin Assignment
Pin Assignment
Pin Assignment
74VHCT540AFT 74VHCT541AFT
6.
6.
6.
6. Marking
Marking
Marking
Marking
74VHCT540AFT 74VHCT541AFT
2017-02-23
Rev.4.0
©2017 Toshiba Corporation
74VHCT540AFT,74VHCT541AFT
3
7.
7.
7.
7. IEC Logic Symbol
IEC Logic Symbol
IEC Logic Symbol
IEC Logic Symbol
74VHCT540AFT 74VHCT541AFT
8.
8.
8.
8. Truth Table
Truth Table
Truth Table
Truth Table
Input G1
H
X
L
L
Input G2
X
H
L
L
Input An
X
X
H
L
Output Yn
Z
Z
H
L
Output Yn
Z
Z
L
H
X: Don't care
Z: High impedance
Yn: 74VHCT541AFT
Yn: 74VHCT540AFT
9.
9.
9.
9. Absolute Maximum Ratings (Note)
Absolute Maximum Ratings (Note)
Absolute Maximum Ratings (Note)
Absolute Maximum Ratings (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Input diode current
Output diode current
Output current
V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Note
(Note1)
(Note2)
(Note3)
(Note4)
Rating
-0.5 to 7.0
-0.5 to 7.0
-0.5 to 7.0
-0.5 to V
CC
+ 0.5
-20
±20
±25
±75
180
-65 to 150
Unit
V
mA
mW
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note1: Output in OFF state.
Note2: High (H) or Low (L) state. I
OUT
absolute maximum rating must be observed.
Note3: V
OUT
< GND, V
OUT
> V
CC
Note4: 180 mW in the range of T
a
= -40 to 85 . From T
a
= 85 to 125 a derating factor of -3.25 mW/ shall be
applied until 50 mW.
2017-02-23
Rev.4.0
©2017 Toshiba Corporation
P1-P3P4-P6P7-P8

74VHCT541AFT

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Manufacturer:
Description:
Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS Automotive T/R
Lifecycle:
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