FAN4800 Low Start-Up Current PFC/PWM Controller Combos
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800 Rev. 1.0.5 10
3. The output of the voltage error amplifier, V
EAO
. The
gain modulator responds linearly to variations in this
voltage.
The output of the gain modulator is a current signal, in
the form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual ground
(negative) input of the current error amplifier. In this way,
the gain modulator forms the reference for the current
error loop and ultimately controls the instantaneous cur-
rent draw of the PFC from the power line. The general
form of the output of the gain modulator is:
More precisely, the output current of the gain modulator
is given by:
where K is in units of V
-1
.
Note that the output current of the gain modulator is lim-
ited around 228.57µA and the maximum output voltage
of the gain modulator is limited to 228.57µA x 3.5K =
0.8V.
This 0.8V also determines the maximum input power.
However, I
GAINMOD
cannot be measured directly from
I
SENSE
. I
SENSE
= I
GAINMOD
– I
OFFSET
and I
OFFSET
can
only be measured when V
EAO
is less than 0.5V and
I
GAINMOD
is 0A. Typical I
OFFSET
is around 60µA.
1.2 Selecting R
AC
for I
AC
pin
I
AC
pin is the input of the gain modulator. I
AC
is also a
current mirror input and requires current input. Selecting
a proper resistor R
AC
provides a good sine wave current
derived from the line voltage and helps program the
maximum input power and minimum input line voltage.
R
AC
= V
IN
peak x 7.9K. For example, if the minimum line
voltage is 80V
AC
, the R
AC
= 80 x 1.414 x 7.9K = 894kΩ.
1.3 Current Error Amplifier, IEAO
The current error amplifier’s output controls the PFC duty
cycle to keep the average current through the boost
inductor a linear function of the line voltage. At the invert-
ing input to the current error amplifier, the output current
of the gain modulator is summed with a current, which
results from a negative voltage being impressed upon
the I
SENSE
pin.
The negative voltage on I
SENSE
represents the sum of all
currents flowing in the PFC circuit and is typically derived
from a current sense resistor in series with the negative
terminal of the input bridge rectifier.
The inverting input of the current error amplifier is a vir-
tual ground. Given this fact, and the arrangement of the
duty cycle modulator polarities internal to the PFC, an
increase in positive current from the gain modulator
causes the output stage to increase its duty cycle until
the voltage on I
SENSE
is adequately negative to cancel
this increased current. Similarly, if the gain modulator’s
output decreases, the output duty cycle decreases to
achieve a less negative voltage on the I
SENSE
pin.
1.4 Cycle-By-Cycle Current Limiter and Selecting R
S
As well as being a part of the current feedback loop, the
I
SENSE
pin is a direct input to the cycle-by-cycle current
limiter for the PFC section. If the input voltage at this pin
is ever less than -1V, the output of the PFC is disabled
until the protection flip-flop is reset by the clock pulse at
the start of the next PFC power cycle.
R
S
is the sensing resistor of the PFC boost converter.
During the steady state, line input current x R
S
equals
I
GAINMOD
x 3.5K.
Since the maximum output voltage of the gain modulator
is I
GAINMOD
maximum x 3.5k = 0.8V during the steady
state, R
S
x line input current is limited to below 0.8V as
well. Therefore, to choose R
S
, use the following equation:
For example, if the minimum input voltage is 80V
AC
and
the maximum input RMS power is 200Watt,
R
S
= (0.8V x 80V x 1.414) / (2 x 200) = 0.226Ω.
1.5 PFC OVP
In the FAN4800, the PFC OVP comparator serves to pro-
tect the power circuit from being subjected to excessive
voltages if the load changes suddenly. A resistor divider
from the high-voltage DC output of the PFC is fed to V
FB
.
When the voltage on V
FB
exceeds 2.78V, the PFC output
driver is shut down. The PWM section continues to oper-
ate. The OVP comparator has 280mV of hysteresis and
the PFC does not restart until the voltage at V
FB
drops
below 2.50V. V
CC
OVP can also serve as a redundant
PFC OVP protection. V
CC
OVP threshold is 17.9V with
1.5V hysteresis.
2
1
AC EAO
GAINMOD
RMS
IV
IV
V
×
(3)
( 0.625)GAINMOD
EAO AC
IKV I ×
(4)
(5)
0.8
2
INPEAK
S
VV
R
LineInput Power
×
=
×
FAN4800 Low Start-Up Current PFC/PWM Controller Combos
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800 Rev. 1.0.5 11
Figure 7. PFC Section Block Diagram
1.6 Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a neg-
ative resistor because an increase in the input voltage to
the PWM causes a decrease in the input current. This
response dictates the proper compensation of the two
transconductance error amplifiers.
Figure 8 shows the types of compensation networks
most commonly used for the voltage and current error
amplifiers, along with their respective return points. The
current-loop compensation is returned to V
REF
to pro-
duce a soft-start characteristic on the PFC: As the refer-
ence voltage increases from 0V, it creates a
differentiated voltage on I
EAO
, which prevents the PFC
from immediately demanding a full duty cycle on its
boost converter.
1.7 PFC Voltage Loop
There are two major concerns when compensating the
voltage loop error amplifier (V
EAO
); stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency half that of the line fre-
quency, or 23Hz for a 47Hz line (lowest anticipated inter-
national power frequency). The gain vs. input voltage of
the FAN4800’s voltage error amplifier (V
EAO
) has a spe-
cially shaped non-linearity, so that under steady-state
operating conditions, the transconductance of the error
amplifier is at a local minimum. Rapid perturbation in line
or load conditions causes the input to the voltage error
amplifier (V
FB
) to deviate from its 2.5V (nominal) value. If
this happens, the transconductance of the voltage error
amplifier increases significantly, as shown in the Figure
4. This raises the gain-bandwidth product of the voltage
loop, resulting in a much more rapid voltage loop
response to such perturbations than would occur with
conventional linear gain characteristics.
The Voltage loop gain(s) is given by:
where:
Z
C
: Compensation network for the voltage loop.
GM
V
: Transconductance of V
EAO
.
P
IN
: Average PFC input power.
V
2
OUTDC
: PFC boost output voltage (typical designed
value is 380V).
C
DC
: PFC boost output capacitor.
1.8 PFC Current Loop
The compensation of the current amplifier (I
EAO
) is simi-
lar to that of the voltage error amplifier (V
EAO
) with the
exception of the choice of crossover frequency. The
crossover frequency of the current amplifier should be at
least ten times that of the voltage amplifier to prevent
interaction with the voltage loop. It should also be limited
to less than one sixth of the switching frequency, e.g.,
16.7kHz for a 100kHz switching frequency.
The current loop gain(s) is given by:
RAMP1
OSCILLATOR
4
3
15
2
POWER FACTOR CORRECTOR
GAIN
MODULATOR
V
FB
7.5V
REFERENCE
7
S
R
Q
S
R
Q
I
EAO
V
EAO
PFC OUT
2.78V
-1V
12
14
0.3V
Low Power
Detector
V
CC
TRI-FAULT
V
CC
OVP
PFC OVP
PFC CMP
CLK
13116
3.5k
3.5k
2.5V
I
AC
I
SENSE
V
RMS
0.5V
17.9V
PFC I
LIMIT
V
CC
V
REF
FAN4800 Rev.02
(6)
OUT EAO
FB
EAO OUT FB
IN
VC
OUTDC EAO DC
VV
V
VV V
PV
GM Z
VVSC
2
2.5
Δ
Δ
Δ
×
ΔΔ Δ
×
≈××
×Δ × ×
(7)
ISENSE OFF EAO
OFF EAO ISENSE
OUTDC S
ICI
VDI
DIV
VR
GM Z
SL V2.5
Δ
ΔΔ
×
ΔΔΔ
×
≈××
××
FAN4800 Low Start-Up Current PFC/PWM Controller Combos
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800 Rev. 1.0.5 12
where:
Z
CI
: Compensation network for the current loop.
GM
I
: Transconductance of I
EAO
.
V
OUTDC
: PFC boost output voltage (typical designed
value is 380V). The equation uses the worst-
case condition to calculate the Z
CI
.
R
S
: Sensing resistor of the boost converter.
2.5V: Amplitude of the PFC leading modulation
ramp.
L: Boost inductor.
A modest degree of gain contouring is applied to the
transfer characteristic of the current error amplifier to
increase its response speed to current-loop perturba-
tions. However, the boost inductor is usually the domi-
nant factor in overall current loop response. Therefore,
this contouring is significantly less marked than that of
the voltage error amplifier. This is illustrated in Figure 8.
Figure 8. Compensation Network Connection for the
Voltage and Current Error Amplifiers
There is an RC filter between R
S
and I
SENSE
pin.
There are two reasons to add a filter at the I
SENSE
pin:
1) Protection: During start-up or in-rush current condi-
tions, there is a large voltage across R
S
, which is the
sensing resistor of the PFC boost converter. It
requires the I
SENSE
filter to attenuate the energy.
2) To reduce L, the boost inductor: The I
SENSE
filter also
can reduce the boost inductor value since the I
SENSE
filter behaves like an integrator before the I
SENSE
pin,
which is the input of the current error amplifier, I
EAO
.
The I
SENSE
filter is an RC filter. The resistor value of
the I
SENSE
filter is between 100Ω and 50Ω because I
OFF-
SET
x R
S
can generate an offset voltage of I
EAO
.
Selecting an R
FILTER
equal to 50Ω keeps the offset of the
I
EAO
less than 5mV. Design the pole of I
SENSE
filter at
f
pfc
/6, one sixth of the PFC switching frequency, so the
boost inductor can be reduced six times without disturb-
ing the stability. The capacitor of the I
SENSE
filter, C
FIL-
TER
, is approximately 283nF.
Figure 9. External Component Connection to V
CC
1.9 Oscillator (RAMP1)
The oscillator frequency is determined by the values of
R
T
and C
T
, which determine the ramp and off-time of the
oscillator output clock:
The dead time of the oscillator is derived from the follow-
ing equation:
at V
REF
= 7.5V and t
RAMP
= C
T
x R
T
x 0.55.
The dead time of the oscillator may be determined using:
The dead time is so small (t
RAMP
>>t
DEAD
) that the oper-
ating frequency can typically be approximated by:
V
RMS
4
3
15
2
Gain
Modulator
V
FB
I
SENSE
I
AC
I
EAO
V
EAO
3.5k
3.5k
2.5V
PFC CMP
1
16
PFC
Output
V
ref
FAN4800 Rev.02
FAN4800
V
CC
GND
V
BIAS
R
BIAS
0.22μF
Ceramic
15V
Zener
FAN4800 Rev.03
(8)
OSC
RAMP DEAD
1
f
tt
=
+
(9)
REF
RAMP T T
REF
V -1.00
tCRln
V -3.75
⎛⎞
×
⎜⎟
⎝⎠
(10)
2.75
DEAD T T
V
tC227C
12.11mA
=×
(11)
OSC
RAMP
1
f
t
=

FAN4800IM

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC CTLR PFC PWM 16-SOIC
Lifecycle:
New from this manufacturer.
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