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whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction
with mission-critical equipment or applications. Any performance specifi cations are believed to be reliable but are not verifi ed, and Buyer must conduct and complete all performance and other testing of the products, alone
and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifi cations or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability
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RJ-45
SFP
1 GbE Line Card
Recovered Clock
Output
SGMII
44
4
2
1
VSC8664
Gigabit
Ethernet
Switch/MAC
Synchronous
Ethernet PLL
CPU
Applications
• Copper and fi ber-based synchronous
Ethernet systems
• SGMII-to-SFP designs
• Multiport, SGMII-based Gigabit Ethernet
(GbE) designs
Low Power
• Low power consumption with three power
savings modes
• ActiPHY™ power management system
with built-in intelligence and saving modes
The industry’s fi rst PHY with dual recovered clock outputs delivers
carrier-quality Synchronous Ethernet.
Helping OEMs to capitalize on the cost reduction and optimization
of Synchronous Ethernet, the VSC8664 addresses the challenges in
providing fully traceable timing across TDM backhaul links, cellular
base stations, and other Synchronous Ethernet applications. With dual
recovered clock outputs, the VSC8664 meets and goes beyond the
requirements of the ITU-T Recommendation G.8261/Y.1361.
Supporting four copper/fi ber ports and SGMII MAC interfaces, the
VSC8664 includes a highly integrated feature set to ensure low-cost,
rapid deployment.
Meeting the carrier demands for redundancy, the VSC8664 features
dual recovered clocks to enable a primary and secondary timing
reference. Programmable clock squelch control is included to inhibit
undesirable clocks from propagating and to help prevent timing loops.
VSC8664 is the fi rst GbE PHY to provide clock recovery in combination
with an SGMII interface, making layouts simpler than RGMII/GMII
solutions. Also featured is a fast link failure indication that can indicate
the onset of a link failure in less than 1 ms, a critical feature for support
of synchronization timing.
VSC8664 helps to lower the component count without sacrifi cing
capabilities or utility, resulting in more cost-effective production and
deployment. Its patented, low electromagnetic interference line driver
and integrated line side termination resistors conserve both power and
printed circuit board space. With an integrated I2C multiplexer to control
SFPs or power-over-Ethernet modules, VSC8664 also eliminates the
need for an external two-wire serial device.
Microsemi's mixed signal and digital signal processing (DSP)
architecture yield robust performance, supporting both full and half
duplex 10BASE-T, 100BASE-TX, and 1000BASE-T over >140 meters
of CAT-5, unshielded twisted pair cable, with industry leading tolerance
to NEXT, FEXT, Echo, and system noise. With dual, high-performance
1.25 Gbps SerDes, VSC8664 maximizes receive jitter tolerance and
minimizes transmit jitter in comparison to single SerDes architectures.
VSC8664
Quad Port 10/100/1000BASE-T PHY and 100BASE-FX/1000BASE-X SerDes with Recovered Clock Outputs
