Typical performances L6935
10/20
Figure 8. Load regulation
-0.3%
-0.2%
-0.1%
0.0%
0.1%
0.2%
0.3%
0.0 0.5 1.0 1.5 2.0 2.5
Output Current [A]
Load Regulation [%
]
VBIAS
= 1.4V, VIN = 2.6V, VOUT
= 2V
-0.3%
-0.2%
-0.1%
0.0%
0.1%
0.2%
0.3%
0.0 0.5 1.0 1.5 2.0 2.5
Output Current [A]
Load Regulation [%
]
VBIAS
= VIN = 1.4V, VOUT
= 0.5V
Device description L6935
11/20
5 Device description
5.1 Soft-start
L6935 implements a soft-start feature to smoothly charge the output filter avoiding high in-
rush currents to be required to the input power supply.
The soft-start process begins as soon as V
BIAS
reaches UVLO and ENABLE is asserted.
A constant current I
SS
= 1.0 µA is sourced through the SS pin: connecting an external
capacitor (C
SS
) to this pin a voltage ramp is implemented; the voltage ramp internally
clamps the E.A. reference, resulting in a controlled slope for the output voltage. As the
voltage on C
SS
reaches the V
REF
value the internal clamp is released.
In this way, the soft-start process lasts for:
where C
SS
is the external capacitor [F] and T
SS
is the soft-start time [sec.].
If the device is disabled (ENABLE low) and the VBIAS is still present, the SS pin is clamped
to GND for a fixed time of about 50 µs. in order to discharge the residual charge present on
C
SS
: in this way, the device will be ready for a new SS process as ENABLE is asserted
again.
Figure 9 describes a typical soft-start process.
Figure 9. Soft start process diagram (left) and measured (right)
T
SS
C
SS
V
REF
I
SS
--------------
510
5
C
SS
F[]⋅⋅==
ENABLE
Vbias
ADJ
Vout
0.5V
>0.7V
>1.1V
Programmed Vout
~50µsec
Programmed Tss
Device description L6935
12/20
5.2 Power Good
L6935 presents a PGOOD flag, an open drain output that is grounded during all the soft
start procedure, and is left free when V
OUT
reaches 90 % of the programmed value.
An hysteresis of 10 % is also provided in order to avoid false triggering due to the noise
generated by the application. Figure 10 shows the PGOOD commutations.
Figure 10. Power good window
5.3 V
IN
vs V
BIAS
L6935 provides the flexibility to supply the internal logic (VBIAS) with a supply different than
the power input (VIN). The aim of this feature is to provide low-drop regulation still having
the supply voltage to correctly drive the internal power mosfet so optimizing the conversion.
VIN drives only the drain of the power DMOS and it can be kept as low as possible
(V
IN
> V
OUT
+ V
DROPmin
), while V
BIAS
drives the control section. V
BIAS
must be typically
higher than V
IN
.
5.4 Protections
L6935 is equipped with a set of protections in order to protect both the load and the device
from electrical overstress. Each protection does not latch the device, that returns to work
properly as the perturbation disappear.
5.4.1 Over-current protection
An over current protection is provided: if the current that flows through the power DMOS is
greater than 3.5 A, the device adjust the power DMOS driving voltage in order to keep
constant the delivered current (I
OUT
). Anyhow the output may drop also causing the
PGOOD to be set low.
Figure 11 show the way the OCP intervention: as the threshold value is reached by I
OUT
, the
device forces a lower output current (~3.5 A).

L6935TR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
LDO Voltage Regulators High Perf 3A Uldo Reg
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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