IRMDSS1 Datasheet IRMDSS1 | P4-P6

IRMDSS1

3 . Setting up the IR 1110 Reference Design for use.

1. Mount the three IRKH Addapaks on a heatsink. A drill plan for

the mounting holes in the heatsink are shown in Fig 4.

The heatsink must be able to maintain the case

temperature of the Addapaks at less than 90°C, at full output

current. Typical losses in each Addapak module, for 3-phase

operation, are given in Table 2.

2. Position the PCB over the Addapak modules, fitting the gate

and auxiliary cathode fast-on terminals attached to the

modules into the slots in the PCB. Insert washers between the

module terminals and the holes in the PCB. Insert M5 screws

with washers through the holes on the PCB, through the

washers on the underside of the PCB, into the terminal holes of

the modules, and tighten. Solder the top stems of the fast-on

terminals into the PCB.

For dc current greater than 40A, remove JP2 and JP3 and

assemble as illustrated in Fig 3.

3. Make electrical connections as shown in Fig 5.

The IR 1110 Reference Design is now ready for use.

4 . Operating features.

4(a) Soft charging of the dc bus capacitor.

When ac input voltage is switched on, the voltage across the dc

bus capacitor ramps up automatically, by phase-control of the SCRs.

The ramp-up rate is determined by capacitor (C24 + C24A). The factory-

fitted value is 3µF. The corresponding ramp-up time is

approximately 330ms.

The ramp-up time can be reduced by reducing the paralleled combination of

C24 and C24A. For example, with C24A removed, and C24 = 1.0uF, the ram-up

time is approximately 150ms.

4(b) Regulation of the dc bus voltage.

The operating bus voltage can be regulated by one of the

following methods:

IRMDSS1

(1) Control of an externally applied 1.4 to 4.0V (nominal) reference

voltage, VBUSREF, applied between JP4/1 and JP4/2. (JP4/1

negative with respect to JP4/2)

For test purposes, the bus voltage can be controlled

manually, by connecting a 50kO potentiometer between JP4/1

and JP4/3, and changing R52 to 4.53k, (1%).

Control of the potentiometer resistance from 0 to 50k

controls VBUSREF from approximately 4.0V to 1.4V . This

controls the dc bus voltage from maximum to approximately

35% of the maximum value obtained at maximum input line

voltage; e.g. for the factory setting of 550V rms maximum

input voltage, the minimum regulated bus voltage is about

270V dc.

It should be noted that the potentiometer floats at the

potential of the positive terminal of the SCR bridge. Care must

be taken to ensure that the knob of the potentiometer is

properly isolated, to avoid the possibility for electrical shock

when manually adjusting the potentiometer.

(2) A PWM signal can be applied to the input of opto-coupler U5,

between JP5/1 and JP5/2, as shown in Fig 6. The opto-coupler

provides isolation between the PWM input source and the

IR 1110, which floats at the potential of the positive terminal of

the rectifier.

The frequency of the PWM signal should be in the 1 to 5kHz

range.

The relationship between the ON/OFF duty cycle, D, of the PWM

input and the dc bus voltage is approximately:

VBUS = VBUSmax (0.35 + 0.65D)

VBUSmax is the maximum bus voltage at maximum input

voltage.

The bus voltage is regulated to within approximately +-8V, for

a change of line voltage of +-80V.

Rise and fall rates of the bus voltage that are driven by

changes in the duty cycle, D, (hence in the average value of

VBUSREF), are determined by the rate of change of D, and by

the load characteristics. The rate of increase of D should be

limited to avoid excessive bus capacitor charging current.

IRMDSS1

4(c) Adjusting the dc loop gain.

The voltage regulation loop can exhibit uneven timing between

successive SCR firing points, with loads that have abnormally high

ripple voltage. Such ripple instability - should it occur - can be

corrected by reducing the dc loop gain.

Remove the zero ohm link R58. Re-insert R58, and insert R54

with values calculated as follows.

The dc loop gain will be reduced by a factor of R54/(R54+R58).

R54 and R58 should be chosen so that their sum is 200-250k Ohms.

4(d) Deactivating the voltage regulation function.

If regulation of the bus voltage is not required, i.e. the rectifier

is always required to deliver maximum possible dc bus voltage in

normal operation, connect JP4/1 to JP4/3.

Note that the soft start function is always activated, whether or not the voltage

regulation function is used.

4(e) Low line voltage.

If the input line voltage falls below the specified minimum

operating value, as shown in Table 1, the rectifier is deactivated by

removal of the SCR firing pulses. When the line voltage returns to

normal, the bus voltage is automatically ramped back to the set

value.

4(f) Temporary loss of all three input line voltages.

When all three input phases are temporarily lost, the dc bus voltage

starts to decreases during the outage.

(a) If the bus voltage does not dip below a set fraction, k, of the

initial operating bus voltage, VBUS1, then when the input

voltage returns, the bus capacitor is recharged without phase-

control of the SCRs. This allows the bus voltage to be restored

as quickly as possible for relatively minor dips of bus voltage,

and minimizes the effect of the line outage on system

operation.

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KIT DESIGN IC REF SOFT START

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