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TOOLSTICK850-B-SK

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
NCV8877
www.onsemi.com
13
Where: P
d
: Power dissipation in the diode [W]
V
f(max)
: Maximum forward voltage of the diode [V]
10. Design Notes
• VOUT serves a dual purpose (feedback and IC power).
The VDRV circuit has a current pulse power draw
resulting in current flow from the output sense location
to the IC. Trace ESL will cause voltage ripple to
develop at IC pin VOUT which could affect
performance.
♦ Use a 1 mF IC VOUT pin decoupling capacitor close
to IC in addition to the VDRV decoupling capacitor.
• Classic feedback loop measurements are not possible
(VOUT pin serves a dual purpose as a feedback path
and IC power). Feedback loop computer modeling
recommended.
♦ A step load test for stability verification is
recommended.
• Compensation ground must be dedicated and connected
directly to IC ground.
♦ Do not use vias. Use a dedicated ground trace.
• ROSC programming resistor ground must be dedicated
and connected directly to IC ground
♦ Do not use vias. Use a dedicated ground trace.
• IC ground & current sense resistor ground sense point
must be located on the same side of PCB.
♦ Vias introduce sufficient ESR/ESL voltage drop
which can degrade the accuracy of the current
feedback signal amplitude (signal bounce) and
should be avoided.
• Star ground should be located at IC ground pad.
♦ This is the location for connecting the compensation
and current sense grounds.
• The IC architecture has a leading edge ISNS blanking
circuit. In some instances, current pulse leading edge
current spike RC filter may be required.
♦ If required, 330 pF + 250 W are a recommended
evaluation starting point.
• R
DAMPING
(optional)
♦ The IC-VOUT pin may be located a few cm from
the output voltage sensing point. Parasitic
inductance from the feedback trace (roughly
5 nH/cm) results in the requirement for a decoupling
capacitor (C
decoupling
= 1 mF recommended) next to
the IC-VOUT pin to support the VDRV charging
pulses. The IC-VDRV energy is replenished from
current pulses by an internal linear regulator whose
charging frequency corresponds to that of the IC
oscillator (phase lag may occur; some charging
pulses may occasionally be skipped depending on
the state of the VDRV voltage). The trace’s parasitic
inductance can introduce a low amplitude damped
voltage oscillation between the IC-VOUT and the
output voltage sense location which may result in
minor frequency jitter.
♦ If the measured frequency jitter is objectionable, it
may be attenuated by placing a series damping
resistor (R
damp
) in the feedback path between the
output voltage sense and IC-VOUT. The resulting
filter introduced by R
damp
introduces a high
frequency pole in the feedback loop path. The RC
filter 3 dB pole frequency must be chosen at a
minimum of 1 decade above the design’s feedback
loop cross-over frequency (at minimum power
supply input voltage where the worst case phase
margin will occur) to avoid deteriorating the
feedback loop cross-over frequency phase margin.
♦ The average operating current demand from the IC
is dominated by the MOSFET gate drive power
energy consumption (I
VDRV
= Q
g
(tot)_6V x f
osc
).
The I
VDRV
x R
damp
voltage drop results in a
corresponding increase in power supply regulation
voltage. R
damp
is typically 0.68 W, so the resulting
increase in output voltage regulation will be minimal
(10-30 mV may be typical).
11. Determine Feedback Loop Compensation Network
The purpose of a compensation network is to stabilize the
dynamic response of the converter. By optimizing the
compensation network, stable regulation response is
achieved for input line and load transients.
Compensator design involves the placement of poles and
zeros in the closed loop transfer function. Losses from the
boost inductor, MOSFET, current sensing and boost diode
losses also influence the gain and compensation
expressions. The OTA has an ESD protection structure
(R
ESD
≈ 502 W, data not provided in the datasheet) located
on the die between the OTA output and the IC package
compensation pin (VC). The information from the OTA
PWM feedback control signal (V
CTRL
) may differ from the
IC−VC signal if R
2
is of similar order of magnitude as R
ESD
.
The compensation and gain expressions which follow take
influence from the OTA output impedance elements into
account.
Type−I compensation is not possible due to the presence
of R
ESD
. The Figure 18 compensation network corresponds
to a Type−II network in series with R
ESD
. The resulting
control−output transfer function is an accurate mathematical
model of the IC in a boost converter topology. The model
does have limitations and a more accurate SPICE model
should be considered for a more detailed analysis:
• The attenuating effect of large value ceramic capacitors
in parallel with output electrolytic capacitor ESR is not
considered in the equations.
• The efficiency term h should be a reasonable operating
condition estimate.
NCV8877
www.onsemi.com
14
Rds(on)
V
d
L
R
i
C
OUT
V
OUT
C
1
R
2
V
IN
r
L
r
Cf
C
2
R
OUT
GND
ISNS
VOUT
GDRV
VC
V
CTRL
OTA
R
ESD
R
1
R
LOW
R
0
V
REF
Figure 18. NCV8877 OTA and Compensation
NRVB440MFS
NVMFS5844NL
A worksheet as well as a SPICE model which may be used
for selecting compensation components R
2
, C
1
, C
2
is
available at the ON Semiconductor web site
(http://onsemi.com/PowerSolutions/product.do?id=NCV8
877). The following equations may be used to analyze the
Figure 10 boost converter. Required input design parameters
for analysis are:
V
d
= Boost diode V
f
(V)
V
IN
= Boost supply input voltage (V)
R
i
= Current sense resistor (W)
R
DS(on)
= MOSFET R
DS(on)
(W)
C
OUT
= Bulk output capacitor value (F)
R
sw_eq
= R
DS(on)
+ R
i
, for the boost continuous
conduction mode (CCM) expressions
r
CF
= Bulk output capacitor ESR (W)
R
OUT
= Equivalent resistance of output load (W)
P
out
= Output Power (W)
L = Boost inductor value (H)
r
L
= Boost inductor ESR (W)
T
s
= 1/f
s
, where f
s
= clock frequency (Hz)
V
OUT
= Device specific output voltage (e.g. 6.8 V
for NCV887701) (V)
V
ref
= OTA internal voltage reference = 1.2 V
R
0
= OTA output resistance = 3 MW
S
a
= IC slope compensation (e.g. 53 mV/ms for
NCV887701)
g
m
= OTA transconductance = 1.2 mS
D = Controller duty ratio
D’ = 1 − D
NCV8877
www.onsemi.com
15
Necessary equations for describing the modulator gain (V
ctrl
−to−V
out
gain) H
ctrl_output(f)
are described in Table 1.
Table 1. BOOST CCM TRANSFER FUNCTION EXPRESSIONS
Duty ratio (D)
ȧ
ȧ
ȧ
ȧ
ȡ
Ȣ
2R
OUT
V
d
V
IN
*
ƪ
R
sw_eq
)R
OUT
ǒ
V
IN
V
OUT
*2
Ǔ
ƫ
V
OUT
2
−V
OUT
R
OUT
ǒ
R
OUT
V
IN
2
)2R
sw_eq
V
IN
V
OUT
*4V
d
R
sw_eq
V
IN
−4R
sw_eq
V
OUT
2
*4r
L
V
d
V
IN
*4r
L
V
OUT
2
Ǔ
)R
sw_eq
2
V
OUT
2
Ǹ
ȧ
ȧ
ȧ
ȧ
ȣ
Ȥ
2R
OUT
ǒ
V
OUT
2
) V
d
V
IN
Ǔ
V
out
/V
in
Power Supply DC Con-
version Ratio (M)
1
1 * D
Average Inductor Current (I
lave
)
P
OUT
V
IN
h
Inductor On−slope (S
n
)
V
IN
* I
Lave
ǒ
r
L
) R
sw_eq
Ǔ
L
R
i
Compensation Ramp (m
c
)
1 )
S
a
S
n
C
out
ESR Zero (w
z1
)
1
r
CF
C
OUT
Right−half−plane Zero (w
z2
)
(
1 * D
)
2
L
ǒ
R
OUT
*
r
CF
R
OUT
r
CF
) R
OUT
Ǔ
*
r
L
L
Low Frequency Modulator Pole
(w
p1
)
2
R
OUT
)
T
s
LM
3
m
c
C
OUT
Sampling Double Pole (w
n
)
p
T
s
Sampling Quality Coefficient (Q
p
)
1
p
(
m
c
(
1 * D
)
* 0.5
)
F
m
1
2M )
R
OUT
T
s
LM
2
ǒ
1
2
)
S
a
S
n
Ǔ
H
d
hR
OUT
R
i
Control−output Transfer Function
(H
ctrl_output
(f))
F
m
H
d
ǒ
1 ) j
2pf
w
z1
Ǔ
ǒ
1 ) j
2pf
w
p1
Ǔ
ǒ
* j
2pf
w
z2
Ǔ
ǒ
1 ) j
2pf
w
n
Q
p
)
ǒ
j
2pf
w
n
Ǔ
2
Ǔ
Once the desired cross−over frequency (f
c
) gain adjustment and necessary phase boost are determined from the H
ctrl_output
(f)
gain and phase plots, the Table 2 equations may be used. It should be noted that minor compensation component value
adjustments may become necessary when R
2
≤ ~10 · R
esd
as a result of approximations for determining components R
2
, C
1
,
C
2
.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

TOOLSTICK850-B-SK

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Development Boards & Kits - 8051 TOOLSTICK850 Starter Kit
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