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MC100LVEL05DTR2G

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 5
1 Publication Order Number:
MC100LVEL05/D
MC100LVEL05
3.3V ECL 2‐Input Differential
AND/NAND
Description
The MC100LVEL05 is a 2-input differential AND/NAND gate. The
device is functionally equivalent to the MC100EL05 device and
operates from a 3.3 V supply voltage. With propagation delays and
output transition times equivalent to the EL05, the LVEL05 is ideally
suited for those applications which require the ultimate in AC
performance at low voltage power supplies.
Because a negative 2-input NAND is equivalent to a 2-input OR
function, the differential inputs and outputs of the device allows the
LVEL05 to also be used as a 2-input differential OR/NOR gate.
Features
• 340 ps Propagation Delay
• High Bandwidth Output Transitions
• ESD Protection:
♦ > 4 kV Human Body Mode
♦ > 200 V Machine Model
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
• Q Output will Default LOW with All Inputs Open or at V
EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity
♦ Level 1 for SOIC−8
♦ Level 3 for TSSOP−8
♦ For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 69 Devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
*For additional marking information, refer to
Application Note AND8002/D
.
MARKING DIAGRAMS*
KV05
ALYWG
G
SOIC−8
D SUFFIX
CASE 751
1
8
TSSOP−8
DT SUFFIX
CASE 948R
1
8
1
8
www.onsemi.com
KVL05
ALYW
G
1
8
(Note: Microdot may be in either location)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M
= Date Code
G = Pb-Free Package
SOIC−8 TSSOP−8
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
ORDERING INFORMATION
Device Package Shipping
†
MC100LVEL05DG SOIC−8
(Pb-Free)
98 Units/Tube
MC100LVEL05DR2G SOIC−8
(Pb-Free)
2500/Tape & Reel
TSSOP−8
(Pb-Free)
MC100LVEL05DTR2G 2500/Tape & Reel
TSSOP−8
(Pb-Free)
MC100LVEL05DTG 100 Units/Tube
MC100LVEL05
www.onsemi.com
2
1
2
3
45
6
7
8D
0
D
0
D
1
D
1
V
EE
Q
Q
V
CC
Figure 1. Logic Diagram and Pinout Assignment
D0, D0; D1, D1 ECL Data Inputs
Q, Q
ECL Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply
Table 1. PIN DESCRIPTION
PIN FUNCTION
Table 2. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Psower Supply V
EE
= 0 V 8 to 0 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −8 to 0 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
≤ V
CC
V
I
≥ V
EE
6 to 0
−6 to 0
V
I
out
Output Current Continuous
Surge
50
100
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 190
130
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 41 to 44 ± 5% °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP−8 185
140
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W
T
sol
Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
MC100LVEL05
www.onsemi.com
3
Table 3. LVPECL DC CHARACTERISTICS (V
CC
= 3.3 V; V
EE
= 0.0 V (Note 1))
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 18 25 18 25 19 26 mA
V
OH
Output HIGH Voltage (Note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV
V
OL
Output LOW Voltage (Note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV
V
IH
Input HIGH Voltage (Single-Ended) 2135 2420 2135 2420 2135 2420 mV
V
IL
Input LOW Voltage (Single-Ended) 1490 1825 1490 1825 1490 1825 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
Vpp < 500 mV
Vpp ≥ 500 mV
1.2
1.5
2.9
2.9
1.1
1.4
2.9
2.9
1.1
1.4
2.9
2.9
V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
2. Outputs are terminated through a 50 ohm resistor to V
CC
− 2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
Table 4. LVNECL DC CHARACTERISTICS (V
CC
= 0.0 V; V
EE
= −3.3 V (Note 1))
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 18 25 18 25 19 26 mA
V
OH
Output HIGH Voltage (Note 2) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV
V
OL
Output LOW Voltage (Note 2) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV
V
IH
Input HIGH Voltage (Single-Ended) −1165 −880 −1165 −880 −1165 −880 mV
V
IL
Input LOW Voltage (Single-Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
Vpp < 500 mV
Vpp ≥ 500 mV
−2.1
−1.8
−0.4
−0.4
−2.2
−1.9
−0.4
−0.4
−2.2
−1.9
−0.4
−0.4
V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
2. Outputs are terminated through a 50 ohm resistor to V
CC
− 2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
P1-P3P4-P6

MC100LVEL05DTR2G

Mfr. #:
Buy MC100LVEL05DTR2G
Manufacturer:
ON Semiconductor
Description:
Logic Gates 3.3V ECL 2-Input Diff AND/NAND
Lifecycle:
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