CTSLV315TG

North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
1
CTSLV31
5
Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator with Gain
SON8, MSOP8
RevB0215
DESCRIPTION
The CTSLV315 is a configurable LVPECL, LVDS buffer & translator IC that is optimized for ultra-low
phase noise and 2.5V-3.3V nominal supply voltage. It is particularly useful in converting crystal or
SAW based oscillators into LVPECL and LVDS outputs for up to 1GHz of bandwidth.
Recommended for applications with signal levels below 0.6 Vp-p. For applications with higher signal
levels that do not require gain, refer to the CTSLV310. CTS encourages the user to try both devices
to determine which is best suited for a particular application.
A configurable IC design capable of providing LVPECL or LVDS outputs, ÷1 or ÷2 function, and active
high or active low enable selection. See Table 1 for details of the configurations options that provide
designers with a single IC buffer/translator solution that is extremely compact, flexible and high
performance.
8 configurations which are determined by the static voltage levels of b-0 and b-1. Table 1 details the
configurations.
BLOCK DIAGRAM
Table 1 - Possible IC Configuration
Configuration Bits Functional Configuration
b-0 b-1 Output Type Enable Polarity Division
Open Open LVPECL Active High ÷1
Open Low LVPECL Active High ÷2
Open High LVPECL Active Low ÷1
Low Open LVPECL Active Low ÷2
Low Low LVDS Active High ÷1
Low High LVDS Active High ÷2
High Open LVDS Active Low ÷1
High Low LVDS Active Low ÷2
High High Not Used Not Used Not Used
FEATURES
2.5V-3.3V Operation
Ultra-Low Phase Noise Floor
o LVPECL -167dBc/Hz
o LVDS -165dBc/Hz
Configurable
o LVPECL or LVDS Output
o ÷1 or ÷2
o Enable Active High or Low
1GHz+ Bandwidth
RoHS Compliant Pb Free Packages
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
2
CTSLV31
5
Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator with Gain
SON8, MSOP8
RevB0215
Input Termination
The D input bias is V
DD
/2 fed through an internal 10k resistor. For clock applications, an input signal of at
least 750m V
PP
ensures the CTSLV15 meets AC specifications. The input should also be AC coupled to
maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and V
DD
without
damage or waveform degradation.
LVPECL Output Termination Techniques
DC Coupling
The LVPECL compatible output stage of the CTSLV315 uses a current drive topology to maximize switching
speed as illustrated below. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an
NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This
produces an output current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through the
output pin. The associated output voltage swings match LVPECL levels when external 50 resistors
terminate the outputs.
Both Q and QN should always be terminated identically to avoid waveform distortion and circulating current
caused by unsymmetrical loads. This rule should be followed even if only one output is in use.
V
DD
V
bp
M1
M2
M3
M4
D
V
bn
M5
21.1mA 21.1mA
16mA
V
TT
= V
DD
-2.0V
Q
QN
50 50
21.1mA - High
5.1mA - Low
External
Circuitry
Output
Stage
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
3
CTSLV31
5
Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator with Gain
SON8, MSOP8
RevB0215
Typical Output Termination
AC Coupling
Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. The
illustration below shows the AC coupling technique. The 200 resistors form the required DC loads, and the
50 resistors provide the AC termination. The parallel combination of the 200 and 50 resistors results in a
net 40 AC load termination. In many cases this will work well. If necessary, the 50 resistors can be
increased to about 56. Alternately, bias tees combined with current setting resistors will eliminate the
lowered AC load impedance. The 50 resistors are typically connected to ground but can be connected to the
bias level needed by the succeeding stage.
AC Termination
LVDS Output Termination Technique
The following LVDS termination is compliant to the LVDS specification TIA/EIA-644A.
LVDS Termination

CTSLV315TG

Mfr. #:
Manufacturer:
CTS Electronic Components
Description:
Clock Buffer Ultra Low PN LVPECL LVDS Buff/Div w/Gain
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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