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PL685-P8-058OC

P1-P3P4-P6P7-P7
(Preliminary) PL685-XX
19MHz to 800MHz Low Phase-Noise XO
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 94 4-0800 • fax +1(4 08) 474- 1000 • www.micrel.com Rev 09/16/11 Page 4
ELECTRICAL SPECIFICATIONS
1. ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN
MAX
UNITS
Supply Voltage
V
DD
4.6
V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5
V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5
V
Storage Temperature
T
S
-65
150
C
Ambient Operating Temperature (industrial temperature)*
T
AI
-40
85
C
Ambient Operating Temperature (commercial temperature)
T
AC
0
70
C
Junction Temperature
T
J
125
C
ESD Protection, Machine Model
200
V
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods m ay cause perma ne nt damage to the
device and affe ct product reliability. Th ese co nd itions represent a st ress r ating only, an d functional operations of the device at t hese or any ot her
conditions above the operational limits noted in t his specification is not im plied. *Operating temperature is guaranteed by desi gn. Parts are teste d to
commercial grade only.
2. GENERAL ELECTRICAL SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current, Dynamic
I
DDQ
LVPECL, 622.08MHz, 3.3V
90
mA
Supply Current, Dynamic
PDB Enabled
PDB = 0, 3.3V
10
uA
Output Enable Time
t
OE
OE logic 0 to logic 1, Ta=25º C.
Add one clock period to this
measurement for a usable clock
output.
50
ns
Power Up Time
T
PU
PDB logic 0 to logic 1, Ta=25º C
10
ms
Operating Voltage
V
DD
LVPECL
2.97
3.63
V
Power Up Ramp Rate
t
PU
Time for V
DD
to reach 90% V
DD
.
Power ramp must be monotonic.
0.1
100
ms
Auto-Calibration Time
t
AC
At power up
10
ms
Output Clock Duty Cycle
@ 50% of output waveform
45
50
55
%
(Preliminary) PL685-XX
19MHz to 800MHz Low Phase-Noise XO
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 94 4-0800 • fax +1(4 08) 474- 1000 • www.micrel.com Rev 09/16/11 Page 5
4. CRYSTAL SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Crystal Resonator Frequency
F
XIN
Parallel Fundamental Mode
19
44
MHz
Crystal Cload
C
L_ Crys ta l
V
DD
= 3.3V, programmable
8
12
pF
Shunt Capacitance
C
0_ Crys ta l
3.5
pF
Recommended ESR
R
E
AT cut , up to 40MHz
50
Ω
AT cut , up to 44MHz
45
Ω
5. JITTER SPECIFICATIONS
PARAMETERS
FREQUENCY
CONDITIONS
MIN
TYP
MAX
UNITS
RMS Phase Jitter
622.08MHz
12kHz to 20MHz, XIN=38.88MHz
0.5
ps
Period Jitter, Pk-to-Pk
622.08MHz
10K cycles, XIN=38.88MHz
30
ps
6. PHASE NOISE SPECIFICATIONS
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz
@10kHz
@100kHz
UNITS
Phase Noise, relative
to carrier (typical)
155.52MHz
-61
-90
-114
-123
-126
dBc/Hz
622.08MHz
-46
-77
-101
-111
-114
7. LVPECL OUTPUTS (Q, QB)
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH
Q, QB
Standard LVPECL Termination,
V
DD
= 3.3V
2.275
2.350
2.420
V
Output Low Voltage
V
OL
1.490
1.600
1.680
V
Output Frequency
F
ou t
3.3V
19
800
MHz
Output Rise, Fall Times
t
r
, t
f
20% - 80% of output waveform
300
500
ps
Output Voltage Swing
V
pp
Q, QB
550
800
930
mV
OUT
OUT
50?
50?
LVPECL Levels Test Circuit
LVPECL Transistion Time Waveform
OUT
OUT
20%
80%
t
R
t
F
VDD
DUTY CYCLE
45 - 55% 55 - 45%
2.0V
50%
(Preliminary) PL685-XX
19MHz to 800MHz Low Phase-Noise XO
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 94 4-0800 • fax +1(4 08) 474- 1000 • www.micrel.com Rev 09/16/11 Page 6
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like
ringing).
- Design long traces (<1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections
bouncing back and forth.
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
the V
DD
pin(s) to limit noise from the power supply
- Multiple V
DD
pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with V
DD
can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1 F for
designs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
TSSOP-16L
Symbol
Dimension in MM
Min.
Max.
A
-
1.20
A1
0.05
0.15
b
0.19
0.30
C
0.09
0.20
D
4.90
5.10
E
4.30
4.50
H
6.20
6.60
L
0.45
0.75
e
0.65 BSC
C
L
A
E
H
D
A1
e
B
P1-P3P4-P6P7-P7

PL685-P8-058OC

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Standard Clock Oscillators High Perf Synthesizer w/LVPECL Output
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