(Preliminary) PL685-XX
19MHz to 800MHz Low Phase-Noise XO
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 94 4-0800 • fax +1(4 08) 474- 1000 • www.micrel.com Rev 09/16/11 Page 3
FUNCTIONAL DESCRIPTION
PL685 family of products is an advanced,
programmable LCVCO clock IC that is designed to
meet the most stringent performance specifications
for phase noise, jitter, and power consumption.
There are two main types of VCOs, a) Ring
Oscillator, b) LC Tank oscillator. An LCVCO is made
up of LC tank oscillator. Although a Ring Oscillator
has very good performance, and has a good tuning
range, its phase noise and jitter performance, in
particular at higher frequencies, degrades.
On the other hand, an LCVCO has an outstanding
phase noise and jitter performance, even at higher
frequencies. PL685 family of products takes
advantage of this state of the art technology, and
incorporates the LC tank on-chip, for optimal
performance.
PL685 family exhibit very low phase noise/phase
jitter and peak to peak jitter, wide tuning range, and
very low-power. All members of the PL685 family
accept a low-cost fundamental crystal input of
19MHz to 44MHz or a reference clock input of up to
800MHz and its flexible core is capable of producing
any output frequency between 19MHz to 800MHz.
PLL Programming
The PLL in the PL685 family is fully programmable.
The PLL is equipped with a Prescaler to divide down
the VCO frequency, and a 5-bit VCO frequency
feedback loop divider (M-Counter). The output of the
PLL is transferred to a 4-bit post VCO divider (P-
Counter), to achieve the desired output frequency.
OE (Output Enable)
The OE pin in PL685 family, through programming,
can be configured to support OE pin activation with a
logic ‘1’ or logic ’0’, to provide you with the desired
enable polarity.
The OE pin incorporates a 60KΩ resistor to either
pull-up or pull-down to the default state when the OE
pin is left open.
