MC14557B
http://onsemi.com
5
SWITCHING CHARACTERISTICS (Note 6) (C
L
= 50 pF, T
A
= 25°C)
Symbol
Characteristic V
DD
Min
Typ
(Note 7)
Max Unit
t
TLH
,
t
THL
Rise and Fall Time, Q or Q Output
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
5
10
15
−
−
−
100
50
40
200
100
80
ns
t
PLH
,
t
PHL
Propagation Delay, Clock or CE to Q or Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 215 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 65 ns
5
10
15
−
−
−
300
130
90
600
260
180
ns
t
PLH
,
t
PHL
Propagation Delay, Reset to Q or Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 215 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 70 ns
5
10
15
−
−
−
300
130
95
600
260
190
ns
t
WH(cl)
Pulse Width, Clock 5
10
15
200
100
75
95
45
35
−
−
−
ns
t
WH(rst)
Pulse Width, Reset 5
10
15
300
140
100
150
70
50
−
−
−
ns
f
cl
Clock Frequency (50% Duty Cycle) 5
10
15
−
−
−
3.0
7.5
13.0
1.7
5.0
6.7
MHz
t
su
Setup Time, A or B to Clock or CE
Worst case condition: L1 = L2 = L4 = L8 =
L16 = L32 = V
SS
(Register Length = 1)
5
10
15
700
290
145
350
130
85
−
−
−
ns
Best case condition: L32 = V
DD
, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
5
10
15
400
165
60
45
5
0
−
−
−
t
h
Hold Time, Clock or CE to A or B
Best case condition: L1 = L2 = L4 = L8 = L16 =
L32 = V
SS
(Register Length = 1)
5
10
15
200
100
10
–150
–60
–50
−
−
−
ns
Worst case condition: L32 = V
DD
, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
5
10
15
400
185
85
50
25
22
−
−
−
t
r
,
t
f
Rise and Fall Time, Clock 5
10
15
No Limit
−
t
r
,
t
f
Rise and Fall Time, Reset or CE 5
10
15
−
−
−
−
−
−
15
5
4
ms
t
rem
Removal Time, Reset to Clock or CE 5
10
15
160
80
70
80
40
35
−
−
−
ns
6. The formulas given are for the typical characteristics only at 25°C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
