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AD7829BRW-1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD7829-1
Rev. 0 | Page 15 of 20
OPERATING MODES
Figure 19 shows the power vs. throughput rate for automatic,
full power-down.
The AD7829-1 has two possible modes of operation, depending
on the state of the
CONVST
pulse approximately 100 ns after the
end of a conversion, that is, upon the rising edge of the
THROUGHPUT (kSPS)
100
10
0
0050100
POWER (mW)
1
200 300 400
0.1
50 150 250 350 450
06179-020
EOC
pulse.
Mode 1 Operation (High-Speed Sampling)
When the AD7829-1 is operated in Mode 1, it is not powered
down between conversions. This mode of operation allows high
throughput rates to be achieved.
Figure 21 shows how this
optimum throughput rate is achieved by bringing
CONVST
high before the end of a conversion, that is, before the
EOC
pulses low. When operating in this mode, a new conversion
should not be initiated until 30 ns after the end of a read
operation. This allows the track/hold to acquire the analog
signal to 0.5 LSB accuracy.
Mode 2 Operation (Automatic Power-Down)
Figure 19. AD7829-1 Power vs. Throughput
When the AD7829-1 is operated in Mode 2 (see Figure 22), it
automatically powers down at the end of a conversion. The
FREQUENCY (kHz)
0
–10
–80
(dB)
–40
–50
–60
–70
–20
–30
0
113
142
170
198
227
255
283
312
340
368
396
425
453
481
510
538
566
595
623
651
680
708
736
765
793
821
850
878
906
935
963
28
57
85
991
2048 POINT FFT
SAMPLING
2MSPS
f
IN
= 200kHz
06179-021
CONVST
signal is brought low to initiate a conversion and is
left logic low until after the
EOC
goes high, that is, approximately
100 ns after the end of the conversion. The state of the
CONVST
signal is sampled at this point (that is, 530 ns maximum after
CONVST
falling edge) and the AD7829-1 powers down as long
as
CONVST
is low. The ADC is powered up again on the rising
edge of the
CONVST
signal. Superior power performance can
be achieved in this mode of operation by powering up the
AD7829-1 only to carry out a conversion. The parallel interface
of the AD7829-1 is still fully operational while the ADCs are
powered down. A read can occur while the part is powered
down, and so it does not necessarily need to be placed within
the
Figure 20. AD7829-1 SNR
EOC
pulse, as shown in Figure 22.
t
2
t
1
t
3
VALID
DATA
CONVST
EOC
CS
RD
DB0 TO DB7
TRACK
HOLD
TRACK
HOLD
120ns
06179-022
Figure 21. Mode 1 Operation
AD7829-1
Rev. 0 | Page 16 of 20
CONVST
EOC
CS
RD
DB0 TO DB7
t
POWER-UP
t
1
VALID
DATA
POWER
DOWN
HERE
06179-023
Figure 22. Mode 2 Operation
AD7829-1
Rev. 0 | Page 17 of 20
EOC
PARALLEL INTERFACE
The parallel interface of the AD7829-1 is eight bits wide. Figure 23
shows a timing diagram illustrating the operational sequence of
the AD7829-1 parallel interface. The multiplexer address is latched
into the AD7829-1 on the falling edge of the
RD
input. The on-
chip track/hold goes into hold mode on the falling edge of
CONVST
. A conversion is also initiated at this point. When the
conversion is complete, the end of conversion line (
EOC
) pulses
low to indicate that new data is available in the output register
of the AD7829-1. The
EOC
pulse stays logic low for a maximum
time of 110 ns.
However, the
pulse can be reset high by a rising edge of
RD EOC
. This line can be used to drive an edge-triggered
interrupt of a microprocessor.
CS RD
and going low accesses
the 8-bit conversion result. It is possible to tie
CS
permanently
low and use only
RD
to access the data. In systems where the
part is interfaced to a gate array or ASIC, this
EOC
pulse can be
applied to the
CS RD
and inputs to latch data out of the
AD7829-1 and into the gate array or ASIC. This means that the
gate array or ASIC does not need any conversion status
recognition logic, and it also eliminates the logic required in the
gate array or ASIC to generate the read signal for the AD7829-1.
CONVST
EOC
CS
RD
DB0 TO DB7
A0 TO A2
t
1
t
4
t
5
t
6
t
7
t
8
t
3
t
9
t
10
t
11
t
12
t
13
VALID
DATA
NEXT
CHANNEL
ADDRESS
t
2
06179-024
Figure 23. AD7829-1 Parallel Port Timing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7829BRW-1

Mfr. #:
Buy AD7829BRW-1
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3V/5V 2MSPS 8-Bit 1-/4-/8-Ch Sampling
Lifecycle:
New from this manufacturer.
Delivery:
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