Data Sheet AD1933
Rev. E | Page 15 of 28
DAISY-CHAIN MODE
The AD1933 also allows a daisy-chain configuration to expand
the system 16 DACs (see Figure 12). In this mode, the DBCLK
frequency is 512 f
S
. The first eight slots of the DAC TDM data
stream belong to the first AD1933 in the chain and the last eight
slots belong to the second AD1933. The second AD1933 is the
device attached to the DSP TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1933 can be configured into a dual-line, DAC TDM mode,
as shown in Figure 13. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1933 in the chain and the last four channels belong to
the second AD1933.
The dual-line, DAC TDM mode can also be used to send data at
a 192 kHz sample rate into the AD1933, as shown in Figure 14.
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 12 for a detailed description of
the function of each pin. See Figure 18 for a typical AD1933
configuration with two external stereo DACs. Figure 15 and
Figure 16 show the serial mode formats. For maximum
flexibility, the polarity of LRCLK and BCLK are programmable.
In these figures, all of the clocks are shown with their normal
polarity. The default mode is I
2
S.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
8 UNUSED SLOTS
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
MSB
DSDATA1 (TDM_IN)
OF THE SECOND AD1933
DSDATA2 (TDM_OUT)
OF THE SECOND AD1933
THIS IS THE TDM
TO THE FIRST AD1933
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
DSP
SECOND
AD1933
FIRST
AD1933
06624-012
Figure 12. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two AD1933 Daisy Chain)
DLRCLK
DBCLK
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1
(IN)
DAC L1 DAC R1 DAC L2 DAC R2 DAC L1 DAC R1 DAC L2 DAC R2
DSDATA3
(IN)
DAC L3 DAC R3 DAC L4 DAC R4 DAC L3 DAC R3 DAC L4 DAC R4
DSDATA2
(OUT)
DAC L1 DAC R1 DAC L2 DAC R2
DSDATA4
(OUT)
DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
DSP
SECOND
AD1933
FIRST
AD1933
MSB
06624-013
Figure 13. Dual-Line, DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two AD1933 Daisy Chain; DSDATA3 and DSDATA4 Are the Daisy Chain)
AD1933 Data Sheet
Rev. E | Page 16 of 28
06624-014
DLRCLK
DBCLK
DSDATA1
DAC L1 DAC R1 DAC L2 DAC R2
DSDATA2
DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
MSB
Figure 14. Dual-Line, DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)
LRCLK
BCLK
SDAT
A
LRCLK
BCLK
SDAT
A
LRCLK
BCLK
SDAT
A
LSB LSB
LSB
LSB
LSB LSB
LEFT CHANNEL RIGHT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
LEFT CHANNEL RIGHT CHANNEL
MSB MSB
MSB
MSB
MSB MSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
I
2
S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LRCLK
BCLK
SDAT
A
LSB LSB
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT
f
S
EXCEPT FOR DSP MODE, WHICH IS 2 ×
f
S
.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
MSB MSB
1/
f
S
06624-015
Figure 15. Stereo Serial Modes
Data Sheet AD1933
Rev. E | Page 17 of 28
DBCLK
DLRCLK
DSDATA
LEFT-JUSTIFIED
MODE
DSDATA
RIGHT-JUSTIFIED
MODE
DSDATA
I
2
S-JUSTIFIED
MODE
t
DLH
t
DBH
t
DBL
t
DLS
t
DDS
MSB
MSB
MSB LSB
MSB–1
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
t
DDH
t
DDS
06624-016
Figure 16. DAC Serial Timing
AUXTDMBCLK
AUXTDMLRCLK
DSDATA1
LEFT-JUSTIFIED
MODE
DSDATA1
RIGHT-JUSTIFIED
MODE
DSDATA1
I
2
S-JUSTIFIED
MODE
t
ABH
LSB
MSB
MSB
MSB
MSB–1
t
ABL
t
ALS
t
ALH
06624-017
Figure 17. AUXTDM Serial Timing

AD1933WBSTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Audio D/A Converter ICs IC 8 CHw/on chip PLL
Lifecycle:
New from this manufacturer.
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