AD5228 Data Sheet
Rev. B | Page 4 of 18
Parameter Symbol Conditions Min Typ
1
Max Unit
DYNAMIC CHARACTERISTICS
4, 9, 10, 11
Built-in Debounce and Settling Time
12
t
DB
6 ms
PU Low Pulse Width
t
PU
12 ms
PD Low Pulse Width
t
PD
12 ms
PU High Repetitive Pulse Width
t
PU_REP
1 μs
PD High Repetitive Pulse Width
t
PD_REP
1 μs
Autoscan Start Time t
AS_START
PU
or PD = 0 V
0.6 0.8 1.2 s
Autoscan Time t
AS
PU
or PD = 0 V
0.16 0.25 0.38 s
Bandwidth –3 dB BW_10 R
AB
= 10 kΩ, midscale 460 kHz
BW_50 R
AB
= 50 kΩ, midscale 100 kHz
BW_100 R
AB
= 100 kΩ, midscale 50 kHz
Total Harmonic Distortion THD
V
A
= 1 V rms, R
AB
= 10 kΩ,
V
B
= 0 V dc, f = 1 kHz
0.05 %
Resistor Noise Voltage e
N_WB
R
WB
= 5 kΩ, f = 1 kHz 14
nV/√Hz
1
Typicals represent average readings at 25°C, V
DD
= 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
4
Guaranteed by design and not subject to production test.
5
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
7
PU
and
PD
have 100 kΩ internal pull-up resistors, I
DD_ACT
= V
DD
/100 kΩ + I
OSC
(internal oscillator operating current) when
PU
or
PD
is connected to ground.
8
P
DISS
is calculated based on I
DD_STBY
× V
DD
only. I
DD_ACT
duration should be short. Users should not hold
PU
or
PD
pin to ground longer than necessary to elevate power
dissipation.
9
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
10
All dynamic characteristics use V
DD
= 5 V.
11
Note that all input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. Switching characteristics are measured
using V
DD
= 5 V.
12
The debouncer keeps monitoring the logic-low level once
PU
is connected to ground. Once the signal lasts longer than 11 ms, the debouncer assumes the last
bounce is met and allows the AD5228 to increment by one step. If the
PU
signal remains at low and reaches t
AS_START
, the
AD5528 increments again, see Figure 7. Similar
characteristics apply to
PD
operation.
INTERFACE TIMING DIAGRAMS
04422-0-004
R
WB
PU
t
DB
t
PU
t
PU_REP
Figure 2. Increment R
WB
in Discrete Steps
04422-0-005
R
WB
PU
t
DB
t
AS
t
AS_START
Figure 3. Increment R
WB
in Autoscan Mode
04422-0-006
R
WB
PU
t
DB
t
PD
t
PD_REP
Figure 4. Decrement R
WB
in Discrete Steps
04422-0-007
R
WB
PD
t
DB
t
AS
t
AS_START
Figure 5. Decrement R
WB
in Autoscan Mode
