AD5228 Data Sheet
Rev. B | Page 12 of 18
If the
PU
button is held for longer than 1 second, continuously
holding it activates autoscan mode such that the AD5228
increments by four R
WB
steps per second (see Figure 3).
Whenever the maximum R
WB
(= R
AB
) is reached, R
WB
stops
incrementing regardless of the state of the
PU
pin. Any continu-
ous holding of the
PU
pin to logic-low simply elevates the supply
current.
When both
PU
and
PD
buttons are pressed, R
WB
decrements
until it stops at zero scale.
All the preceding descriptions apply to
PD
operation. Due to
the tolerance of the internal RC oscillator, all the timing
information given previously is based on the typical values,
which can vary ±30%.
The AD5228 debouncer is carefully designed to handle common
pushbutton tactile switches. Other switches that have excessive
bounces and duration are not suitable to use in conjunction
with the AD5228.
04422-0-035
B
W
A
D0
D2
D1
D4
D3
R
S
R
S
=
R
AB
/32
R
W
R
S
R
S
R
S
RDAC
UP/DOWN
CTRL AND
DECODE
Figure 34. AD5228 Equivalent RDAC Circuit
PROGRAMMING THE DIGITAL POTENTIOMETERS
Rheostat Operation
If only the W-to-B or W-to-A terminals are used as variable
resistors, the unused terminal can be opened or shorted with W.
Such operation is called rheostat mode and is shown in Figure 35.
04422-0-036
A
W
B
A
W
B
A
W
B
Figure 35. Rheostat Mode Configuration
The end-to-end resistance, R
AB
, has 32 contact points accessed
by the wiper terminal, plus the B terminal contact if R
WB
is used.
Pushing the
PU
pin discretely increments R
WB
by one step. The
total resistance becomes R
S
+ R
W
as shown in Figure 34. The
change of R
WB
can be determined by the number of discrete
PU
executions provided that its maximum setting is not reached
during operation. R
WB
can, therefore, be approximated as
W
AB
WB
R
R
PUR
32
(1)
W
AB
WB
R
R
PDR
32
(2)
where:
PU
is the number of push-up executions.
PD
is the number of push-down executions.
R
AB
is the end-to-end resistance.
R
W
is the wiper resistance contributed by the on-resistance of
the internal switch.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
complementary resistance, R
WA
. When these terminals are used,
the B terminal can be opened or shorted to W. R
WA
can also be
approximated if its maximum and minimum settings are not
reached.
W
AB
WA
R
R
PUR
32
32
3)
W
AB
WA
R
R
PDR
32
32
(4)
Note that Equations 1 to 4 do not apply when
PU
and
PD
= 0
execution.
Because in the lowest end of the resistor string, a finite wiper
resistance is present, care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switches can occur.
The typical distribution of the resistance tolerance from device
to device is process lot dependent, and ±20% tolerance is possible.
Data Sheet AD5228
Rev. B | Page 13 of 18
Potentiometer Mode Operation
If all three terminals are used, the operation is called potenti-
ometer mode. The most common configuration is the voltage
divider operation as shown in Figure 36.
04422-0-037
A
W
B
V
I
V
C
Figure 36. Potentiometer Mode Configuration
The change of V
WB
is known provided that the AD5228
maximum or minimum scale has not been reached during
operation. If the effect of wiper resistance is ignored, the
transfer functions can be simplified as
AWB
V
PU
V
32
(5)
AWB
V
PD
V
32
(6)
Unlike in rheostat mode operation where the absolute tolerance
is high, potentiometer mode operation yields an almost ratio-
metric function of
PU
/32 or
PD
/32 with a relatively small error
contributed by the R
W
term. The tolerance effect is, therefore,
almost canceled. Although the thin film step resistor R
S
and
CMOS switch resistance, R
W
, have very different temperature
coefficients, the ratiometric adjustment also reduces the overall
temperature coefficient effect to 5 ppm/°C except at low value
codes where R
W
dominates.
Potentiometer mode operations include an op amp input and
feedback resistors network and other voltage scaling applications.
The A, W, and B terminals can be input or output terminals and
have no polarity constraint provided that |V
AB
|, |V
WA
|, and |V
WB
|
do not exceed V
DD
-to-GND.
CONTROLLING INPUTS
All
PU
and
PD
inputs are protected with a Zener ESD structure
as shown in Figure 37.
04422-0-038
V
DD
PU
100k
DECODE
AND
DEBOUNCE
CKT
Figure 37. Equivalent ESD Protection in
PU
and
PD
Pins
PU
and
PD
pins are usually connected to pushbutton tactile
switches for manual operation, but the AD5228 can also be
controlled digitally. It is recommended to add external
MOSFETs or transistors that simplify the logic controls.
04422-0-039
UP/DOWN
CONTROL
LOGIC
DISCRETE
STEP/AUTO
SCAN DETECT
ADAPTIVE
DEBOUNCER
ZERO- OR MID-
SCALE PRESET
AD5228
R1 R2
D
E
C
O
D
E
A
W
B
V
DD
PRE GND
PU
PD
DOWN
N2
2N7002
UP
N1
2N7002
Figure 38. Digital Control with External MOSFETs
TERMINAL VOLTAGE OPERATION RANGE
The AD5228 is designed with internal ESD diodes for
protection. These diodes also set the voltage boundary of the
terminal operating voltages. Positive signals present on
Terminal A, B, or W that exceed V
DD
are clamped by the
forward-biased diode. There is no polarity constraint between
V
A
, V
W
, and V
B
, but they cannot be higher than V
DD
or lower
than GND.
0
4422-0-040
V
DD
GND
A
W
B
Figure 39. Maximum Terminal Voltages Set by V
DD
and GND
AD5228 Data Sheet
Rev. B | Page 14 of 18
POWER-UP AND POWER-DOWN SEQUENCES
Because of the ESD protection diodes that limit the voltage
compliance at Terminals A, B, and W (Figure 39), it is
important to power on V
DD
before applying any voltage to
Terminals A, B, and W. Otherwise, the diodes are forward-
biased such that V
DD
is powered on unintentionally and can
affect other parts of the circuit. Similarly, V
DD
should be
powered down last. The ideal power-on sequence is in the
following order: GND, V
DD
, and V
A/B/W
. The order of powering
V
A
, V
B
, and V
W
is not important as long as they are powered on
after V
DD
. The states of the
PU
and
PD
pins can be logic high or
floating, but they should not be logic low during power-on.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Low ESR (equivalent series resistance) 1 μF to 10 μF tantalum
or electrolytic capacitors should be applied at the supplies to
minimize any transient disturbance and to filter low frequency
ripple. Figure 39 illustrates the basic supply bypassing configu-
ration for the AD5228.
04422-0-041
V
DD
V
DD
+
GND
AD5228
C2
10F
C1
0.1F
Figure 40. Power Supply Bypassing

AD5228BUJZ10-RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Potentiometer ICs IC 5-Bit PB Up/Down
Lifecycle:
New from this manufacturer.
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