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X4643S8-4.5A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
16
FN8123.0
March 29, 2005
TIMING DIAGRAMS
Bus Timing
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Notes: (1) t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Symbol Parameter Min. Typ.
(1)
Max. Unit
t
WC
(1)
Write Cycle Time 5 10 ms
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
AA
t
R
t
HD:WP
SCL
SDA IN
WP
t
SU:WP
Clk 1 Clk 9
Slave Address Byte
START
SCL
SDA
t
WC
8th bit of Last Byte ACK
Stop
Condition
Start
Condition
X4643, X4645
17
FN8123.0
March 29, 2005
Power-Up and Power-Down Timing
RESET
Output Timing
Notes: (8) This parameter is periodically sampled and not 100% tested.
SDA vs. RESET Timing
Symbol Parameter Min. Typ. Max. Unit
V
TRIP
Reset Trip Point Voltage, X4643/5-4.5A
Reset Trip Point Voltage, X4643/5
Reset Trip Point Voltage, X4643/5-2.7A
Reset Trip Point Voltage, X4643/5-2.7
4.5
4.25
2.85
2.55
4.62
4.38
2.92
2.62
4.75
4.5
3.0
2.7
V
t
PURST
Power-up Reset Time Out 100 250 400 ms
t
RPD
(8)
V
CC
Detect to Reset/Output 500 ns
t
F
(8)
V
CC
Fall Time 100 µs
t
R
(8)
V
CC
Rise Time 100 µs
V
RVALID
Reset Valid V
CC
1V
V
CC
t
PURST
t
R
t
F
t
RPD
0 Volts
V
TRIP
RESET
RESET
V
RVALID
(X4645)
(X4643)
t
PURST
V
RVALID
t
RSP
<t
WDO
t
RST
RESET
SDA
t
RSP
Note: All inputs are ignored during the active reset period (t
RST
).
t
RST
SCL
t
RSP
>t
WDO
t
RSP
>t
WDO
X4643, X4645
18
FN8123.0
March 29, 2005
RESET Output Timing
V
TRIP
Programming Timing Diagram (WEL = 1)
V
TRIP
Programming Parameters
Symbol Parameter Min. Typ. Max. Unit
t
WDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
OFF
250
650
1.5
300
850
2
ms
ms
sec
t
RST
Reset Time Out 100 250 400 ms
Parameter Description Min. Max. Unit
t
VPS
V
TRIP
Program Enable Voltage Setup time 1 µs
t
VPH
V
TRIP
Program Enable Voltage Hold time 1 µs
t
TSU
V
TRIP
Setup time 1 µs
t
THD
V
TRIP
Hold (stable) time 10 ms
t
WC
V
TRIP
Write Cycle Time 10 ms
t
VPO
V
TRIP
Program Enable Voltage Off time (Between successive adjustments) 0 µs
t
RP
V
TRIP
Program Recovery Period (Between successive adjustments) 10 ms
V
P
Programming Voltage 15 18 V
V
TRAN
V
TRIP
Programmed Voltage Range 2.55 4.75 V
V
ta1
Initial V
TRIP
Program Voltage accuracy (V
CC
applied-V
TRIP
) (Programmed at 25°C.) -0.1 +0.4 V
V
ta2
Subsequent V
TRIP
Program Voltage accuracy [(V
CC
applied-V
ta1
)-V
TRIP
.
Programmed at 25°C.]
-25 +25 mV
V
tr
V
TRIP
Program Voltage repeatability (Successive program operations. Programmed at
25°C.)
-25 +25 mV
V
tv
V
TRIP
Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 mV
V
TRIP
programming parameters are periodically sampled and are not 100% tested.
V
CC
(V
TRIP
)
WP
t
TSU
t
THD
t
VPH
t
VPS
V
P
V
TRIP
t
VPO
SCL
SDA
A0h
01h or 03h
t
RP
00h
00h
X4643, X4645
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

X4643S8-4.5A

Mfr. #:
Buy X4643S8-4.5A
Manufacturer:
Renesas / Intersil
Description:
IC SUPERVISOR CPU 64K EE 8-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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