7
LT1739
1739fas, sn1739
APPLICATIO S I FOR ATIO
WUUU
The LT1739 is a high speed, 200MHz gain bandwidth
product, dual voltage feedback amplifier with high output
current drive capability, 500mA source and sink. The
LT1739 is ideal for use as a line driver in xDSL data
communication applications. The output voltage swing
has been optimized to provide sufficient headroom when
operating from ±12V power supplies in full-rate ADSL
applications. The LT1739 also allows for an adjustment of
the operating current to minimize power consumption. In
addition, the LT1739 is available in small footprint
3mm × 4mm DFN and 20-lead TSSOP surface mount
package to minimize PCB area in multiport central office
DSL cards.
To minimize signal distortion, the LT1739 amplifiers are
decompensated to provide very high open-loop gain at
high frequency. As a result each amplifier is frequency
stable with a closed-loop gain of 10 or more. If a closed-
loop gain of less than 10 is desired, external frequency
compensating components can be used.
Setting the Quiescent Operating Current
Power consumption and dissipation are critical concerns
in multiport xDSL applications. Two pins, Shutdown
(SHDN) and Shutdown Reference (SHDNREF), are pro-
vided to control quiescent power consumption and allow
for the complete shutdown of the driver. The quiescent
current should be set high enough to prevent distortion
induced errors in a particular application, but not so high
that power is wasted in the driver unnecessarily. A good
starting point to evaluate the LT1739 is to set the quiescent
current to 10mA per amplifier.
The internal biasing circuitry is shown in Figure 1. Ground-
ing the SHDNREF pin and directly driving the SHDN pin with
a voltage can control the operating current as seen in the
Typical Performance Characteristics. When the SHDN pin
is less than SHDNREF + 0.4V, the driver is shut down and
consumes typically only 100µA of supply current and the
outputs are in a high impedance state. Part to part varia-
tions, however, will cause inconsistent control of the qui-
escent current if direct voltage drive of the SHDN pin is used.
Using a single external resistor, R
BIAS
, connected in one of
two ways provides a much more predictable control of the
quiescent supply current. Figure 2 illustrates the effect
on supply current per amplifier with R
BIAS
connected
between the SHDN pin and the 12V V
+
supply of the
LT1739 and the approximate design equations. Figure 3
illustrates the same control with R
BIAS
connected between
the SHDNREF pin and ground while the SHDN pin is tied
to V
+
. Either approach is equally effective.
Figure 1. Internal Current Biasing Circuitry
2k
SHDN
SHDNREF
TO
START-UP
CIRCUITRY
1k
1739 F01
I
BIAS
TO AMPLIFIERS
BIAS CIRCUITRY
2I
I
2I
5I
2
5
I
BIAS
=
I
SUPPLY
PER AMPLIFIER (mA) = 64 • I
BIAS
I
SHDN
= I
SHDNREF
R
BIAS
(k)
0
I
SUPPLY
PER AMPLIFIER (mA)
10
20
30
5
15
25
10
1739 F02
7 40 70 100 130 160 190
V
S
= ±12V
V
+
= 12V
R
BIAS
SHDN
SHDNREF
R
BIAS
=
• 25.6 – 2k
V
+
– 1.2V
I
S
PER AMPLIFIER (mA)
I
S
PER AMPLIFIER
(mA)
• 25.6
V
+
– 1.2V
R
BIAS
+ 2k
R
BIAS
(k)
4 7 10 50 90 130 170 210 25030 70 100 150 190 230 270 290
I
SUPPLY
PER AMPLIFIER (mA)
20
25
30
35
40
1739 F03
5
10
15
0
45
V
S
= ±12V
V
+
= 12V
R
BIAS
SHDN
SHDNREF
R
BIAS
=
• 64 – 5k
V
+
– 1.2V
I
S
PER AMPLIFIER (mA)
I
S
PER AMPLIFIER
(mA)
• 64
V
+
– 1.2V
R
BIAS
+ 5k
Figure 2. R
BIAS
to V
+
Current Control
Figure 3. R
BIAS
to Ground Current Control
8
LT1739
1739fas, sn1739
Two Control Inputs
RESISTOR VALUES (k)
R
SHDN
TO V
CC
(12V) R
SHDN
TO V
LOGIC
V
LOGIC
R
SHDN
R
C1
R
CO
3V
40.2
11.5
19.1
3.3V
43.2
13.0
22.1
5V
60.4
21.5
36.5
3V
4.99
8.66
14.3
3.3V
6.81
10.7
17.8
5V
19.6
20.5
34.0
V
C0
H
L
H
L
V
C1
H
H
L
L
10
7
5
2
10
7
5
2
10
7
5
2
10
7
5
2
10
7
5
2
10
7
5
2
SUPPLY CURRENT PER AMPLIFIER (mA)
One Control Input
RESISTOR VALUES (k)
R
SHDN
TO V
CC
(12V) R
SHDN
TO V
LOGIC
V
LOGIC
R
SHDN
R
C
3V
40.2
7.32
3.3V
43.2
8.25
5V
60.4
13.7
3V
4.99
5.49
3.3V
6.81
6.65
5V
19.6
12.7
V
C
H
L
10
2
10
2
10
2
10
2
10
2
10
2
SUPPLY CURRENT PER AMPLIFIER (mA)
R
SHDN
R
C1
V
C1
V
LOGIC
12V OR V
LOGIC
0V
V
C0
R
C0
SHDN
SHDNREF
2k
R
SHDN
R
C
V
C
V
LOGIC
12V OR V
LOGIC
0V
SHDN
SHDNREF
1739 F04
2k
APPLICATIO S I FOR ATIO
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Logic Controlled Operating Current
The DSP controller in a typical xDSL application can have
I/O pins assigned to provide logic control of the LT1739
line driver operating current. As shown in Figure 4 one or
two logic control inputs can set two or four different
operating modes. The logic inputs add or subtract current
to the SHDN input to set the operating current. The one
logic input example selects the supply current to be either
full power, 10mA per amplifier or just 2mA per amplifier,
which significantly reduces the driver power consumption
while maintaining less than 2 output impedance to
frequencies less than 1MHz. This low power mode retains
termination impedance at the amplifier outputs and the
line driving back termination resistors. With this termina-
tion, while a DSL port is not transmitting data, it can still
sense a received signal from the line across the back-
termination resistors and respond accordingly.
The two logic input control provides two intermediate
(approximately 7mA per amplifier and 5mA per amplifier)
operating levels between full power and termination
modes. For proper operation of the current control cir-
cuitry, it is necessary that the SHDNREF pin be biased at
least 2V more positive than V
. In single supply applica-
tions where V
is at ground potential, special attention to
the DC bias of the SHDNREF pin is required. Contact
Linear Technology for assistance in implementing a single
supply design with operating current control. These
modes can be useful for overall system power manage-
ment when full power transmissions are not necessary.
Shutdown and Recovery
The ultimate power saving action on a completely idle port
is to fully shut down the line driver by pulling the SHDN pin
to within 0.4V of the SHDNREF potential. As shown in
Figure 5 complete shutdown occurs in less than 10µs and,
more importantly, complete recovery from the shut down
state to full operation occurs in less than 2µs. The biasing
circuitry in the LT1739 reacts very quickly to bring the
amplifiers back to normal operation.
Figure 4. Providing Logic Input Control of Operating Current
V
SHDN
SHDNREF = 0V
AMPLIFIER
OUTPUT
1794 F05
Figure 5. Shutdown and Recovery Timing
Power Dissipation and Heat Management
xDSL applications require the line driver to dissipate a
significant amount of power and heat compared to other
components in the system. The large peak to RMS varia-
tions of DMT and CAP ADSL signals require high supply
voltages to prevent clipping, and the use of a step-up
transformer to couple the signal to the telephone line can
require high peak current levels. These requirements
result in the driver package having to dissipate significant
amounts of power. Several multiport cards inserted into
a rack in an enclosed central office box can add up to
many, many watts of power dissipation in an elevated
ambient temperature environment. The LT1739 has built-
in thermal shutdown cir
cuitry that will protect the ampli-
fiers if operated at excessive temperatures, however data
transmissions will be seriously impaired. It is important in
9
LT1739
1739fas, sn1739
the design of the PCB and card enclosure to take measures
to spread the heat developed in the driver away to the
ambient environment to prevent thermal shutdown (which
occurs when the junction temperature of the LT1739
exceeds 165°C).
Estimating Line Driver Power Dissipation
Figure 6 is a typical ADSL application shown for the
purpose of estimating the power dissipation in the line
driver. Due to the complex nature of the DMT signal,
which looks very much like noise, it is easiest to use the
RMS values of voltages and currents for estimating the
driver power dissipation. The voltage and current levels
shown for this example are for a full-rate ADSL signal
driving 20dBm or 100mW
RMS
of power on to the 100
telephone line and assuming a 0.5dBm insertion loss in
the transformer. The quiescent current for the LT1739 is
set to 10mA per amplifier.
The power dissipated in the LT1739 is a combination of the
quiescent power and the output stage power when driving
a signal. The two amplifiers are configured to place a
differential signal on to the line. The Class AB output stage
in each amplifier will simultaneously dissipate power in
the upper power transistor of one amplifier, while sourc-
ing current, and the lower power transistor of the other
amplifier, while sinking current. The total device power
dissipation is then:
P
D
= P
QUIESCENT
+ P
Q(UPPER)
+ P
Q(LOWER)
P
D
= (V
+
– V
) • I
Q
+ (V
+
– V
OUTARMS
) •
I
LOAD
+ (V
– V
OUTBRMS
) • I
LOAD
With no signal being placed on the line and the amplifier
biased for 10mA per amplifier supply current, the quies-
cent driver power dissipation is:
P
DQ
= 24V • 20mA = 480mW
This can be reduced in many applications by operating
with a lower quiescent current value.
When driving a load, a large percentage of the amplifier
quiescent current is diverted to the output stage and
becomes part of the load current. Figure 7 illustrates the
total amount of biasing current flowing between the + and
– power supplies through the amplifiers as a function of
load current. As much as 60% of the quiescent no load
operating current is diverted to the load.
APPLICATIO S I FOR ATIO
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Figure 6. Estimating Line Driver Power Dissipation
1739 F06
+
B
–IN
+
A
+IN
12V
20mA DC
SHDN
12V
–2V
RMS
17.4
24.9k – SETS I
Q
PER AMPLIFIER = 10mA
1:1.7
110
1000pF
110
1k
1k
17.4
SHDNREF
100 3.16V
RMS
I
LOAD
= 57mA
RMS
2V
RMS

LT1739CFE#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers 2x 500mA, 200MHz xDSL Line Drvr Amp
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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