AD7856
–21–REV. A
POWER – mW
0.1
10
100
THROUGHPUT – kSPS
0
10 20 30 40 50
1
Figure 24. Power vs. Throughput Rate (6 MHz CLK)
CALIBRATION SECTION
Calibration Overview
The automatic calibration that is performed on power up en-
sures that the calibration options covered in this section will not
be required in a significant amount of applications. The user
will not have to initiate a calibration unless the operating condi-
tions change (CLKIN frequency, analog input mode, reference
voltage, temperature, and supply voltages). The AD7856 has a
number of calibration features that may be required in some
applications and there are a number of advantages in performing
these different types of calibration. First, the internal errors in
the ADC can be reduced significantly to give superior dc perfor-
mance, and secondly, system offset and gain errors can be re-
moved. This allows the user to remove reference errors (whether
it be internal or external reference) and to make use of the full
dynamic range of the AD7856 by adjusting the analog input
range of the part for a specific system.
There are two main calibration modes on the AD7856, self-
calibration and system calibration. There are various options in
both self-calibration and system calibration as outlined previ-
ously in Table IV. All the calibration functions can be initiated
by pulsing the CAL pin or by writing to the control register and
setting the STCAL bit to one. The timing diagrams that follow
involve using the CAL pin.
The duration of each of the different types of calibrations is
given in Table VIII for the AD7856 with a 6 MHz master clock.
These calibration times are master clock dependent.
Table VIII. Calibration Times (AD7856 with 6 MHz CLKIN)
Type of Self- or
System Calibration Time
Full 41.7 ms
Offset + Gain 9.26 ms
Offset 4.63 ms
Gain 4.63 ms
Automatic Calibration on Power-On
The CAL pin has a 0.15 µA pull up current source connected to
it internally to allow for an automatic full self-calibration on
power-on. A full self-calibration will be initiated on power-on if
a capacitor is connected from the CAL pin to DGND. The
internal current source connected to the CAL pin charges up
the external capacitor and the time required to charge the exter-
nal capacitor will depend on the size of the capacitor itself. This
time should be large enough to ensure that the internal refer-
ence is settled before the calibration is performed. A 33 nF
capacitor is sufficient to ensure that the internal reference has
settled (see Power-Up Times) before a calibration is initiated
taking into account trigger level and current source variations on
the CAL pin. However, if an external reference is being used,
this reference must have stabilized before the automatic calibra-
tion is initiated (a larger capacitor on the CAL pin should be
used if the external reference has not settled when the autocali-
bration is initiated). Once the capacitor on the CAL pin has
charged, the calibration will be performed which will take 42 ms
(6 MHz CLKIN). Therefore the autocalibration should be
complete before operating the part. After calibration, the part is
accurate to the 14-bit level and the specifications quoted on the
data sheet apply. There will be no need to perform another
calibration unless the operating conditions change or unless a
system calibration is required.
Self-Calibration Description
There are four different calibration options within the self-
calibration mode. First, there is a full self-calibration where the
DAC, internal gain, and internal offset errors are calibrated out.
Then, there is the (Gain + Offset) self-calibration which cali-
brates out the internal gain error and then the internal offset
errors. The internal DAC is not calibrated here. Finally, there
are the self-offset and self-gain calibrations which calibrate out
the internal offset errors and the internal gain errors respectively.
The internal capacitor DAC is calibrated by trimming each of
the capacitors in the DAC. It is the ratio of these capacitors to
each other that is critical, and so the calibration algorithm en-
sures that this ratio is at a specific value by the end of the cali-
bration routine. For the offset and gain there are two separate
capacitors, one of which is trimmed when an offset or gain cali-
bration is performed. Again, it is the ratio of these capacitors to
the capacitors in the DAC that is critical and the calibration
algorithm ensures that this ratio is at a specified value for both
the offset and gain calibrations.
The zero-scale error is adjusted for an offset calibration, and the
positive full-scale error is adjusted for a gain calibration.
Self-Calibration Timing
The diagram of Figure 25 shows the timing for a full self-
calibration. Here the BUSY line stays high for the full length of
the self-calibration. A self-calibration is initiated by bringing the
CAL pin low (which initiates an internal reset) and then high
again or by writing to the control register and setting the STCAL
bit to 1 (note that if the part is in a power-down mode the CAL pulse -
width must take account of the power-up time ). The BUSY line is
triggered high from the rising edge of CAL (or the end of the
write to the control register if calibration is initiated in soft-
ware), and BUSY will go low when the full-self calibration is
complete after a time t
CAL
as shown in Figure 25.
For the self- (gain + offset), self-offset and self-gain calibrations
the BUSY line will be triggered high by the rising edge of the
CAL signal (or the end of the write to the control register if
calibration is initiated in software) and will stay high for the
full duration of the self calibration. The length of time that
the BUSY is high will depend on the type of self-calibration that
AD7856
–22–
REV. A
is initiated. Typical figures are given in Table VIII. The timing
diagrams for the other self-calibration options will be similar to
that outlined in Figure 25.
t
1
= 100ns MIN,
t
15
= 2.5
t
CLKIN
MAX,
t
CAL
= 250026
t
CLKIN
CAL (I/P)
BUSY (O/P)
t
1
t
15
t
CAL
Figure 25. Timing Diagram for Full-Self Calibration
System Calibration Description
System calibration allows the user to take out system errors
external to the AD7856 as well as calibrate the errors of the
AD7856 itself. The maximum calibration range specified for the
system offset errors is ±3.75% of V
REF
but typically is ±5% and
for the system gain errors is ±1.875% of V
REF
. Therefore, under
worst case conditions the maximum allowable system offset
voltage applied between AIN(+) and AIN(–) would be ±0.0375
× V
REF
, but under typical conditions this means that the maxi-
mum allowable system offset voltage applied between the AIN(+)
and AIN(–) pins for the calibration to adjust out this error is
±0.05
×
V
REF
(i.e., the AIN(+) can be 0.05
×
V
REF
above AIN(–)
or 0.05
×
V
REF
below AIN(–)). For the System gain error the
maximum allowable system full-scale voltage that can be applied
between AIN(+) and AIN(–) for the calibration to adjust out
this error is V
REF
± 0.01875
×
V
REF
(i.e., the AIN(+) can be V
REF
+ 0.01875
×
V
REF
above AIN(–) or V
REF
– 0.01875
×
V
REF
above
AIN(–)). If the system offset or system gain errors are outside
the ranges mentioned the system calibration algorithm will
reduce the errors as much as the trim range allows.
Figures 26 through 28 illustrate why a specific type of system
calibration might be used. Figure 26 shows a system offset cali-
bration (assuming a positive offset) where the analog input
range has been shifted upward by the system offset after the
system offset calibration is completed. A negative offset may
also be accounted for by a system offset calibration.
SYSTEM OFFSET
CALIBRATION
SYS OFFSET
V
REF
– 1LSB
AGND
MAX SYSTEM OFFSET
IS 65% OF V
REF
MAX SYSTEM FULL SCALE
IS 61.875% FROM V
REF
ANALOG
INPUT
RANGE
V
REF
– 1LSB
ANALOG
INPUT
RANGE
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS 65% OF V
REF
V
REF
+ SYS OFFSET
Figure 26. System Offset Calibration
Figure 27 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for by a system gain calibration.
SYSTEM GAIN
CALIBRATION
V
REF
– 1LSB
AGND
MAX SYSTEM FULL SCALE
IS 61.875% FROM V
REF
ANALOG
INPUT
RANGE
V
REF
– 1LSB
ANALOG
INPUT
RANGE
AGND
SYS FS
SYS FS
MAX SYSTEM FULL SCALE
IS 61.875% FROM V
REF
Figure 27. System Gain Calibration
Finally, in Figure 28 both the system offset and gain are ac-
counted for by the system offset followed by a system gain cali-
bration. First, the analog input range is shifted upward by the
positive system offset and then the analog input range is ad-
justed at the top end to account for the system full scale.
SYSTEM OFFSET
CALIBRATION
FOLLOWED BY
SYSTEM GAIN
CALIBRATION
SYS OFFSET
V
REF
– 1LSB
AGND
MAX SYSTEM OFFSET
IS 65% OF V
REF
MAX SYSTEM FULL SCALE
IS 61.875% FROM V
REF
ANALOG
INPUT
RANGE
V
REF
– 1LSB
ANALOG
INPUT
RANGE
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS 65% OF V
REF
V
REF
+ SYS OFFSET
SYS FS
MAX SYSTEM FULL SCALE
IS 61.875% FROM V
REF
SYS FS
Figure 28. System (Gain + Offset) Calibration
System Gain and Offset Interaction
The inherent architecture of the AD7856 leads to an interaction
between the system offset and gain errors when a system calibra-
tion is performed. Therefore, it is recommended to perform the
cycle of a system offset calibration followed by a system gain
calibration twice. Separate system offset and system gain cali-
brations reduce the offset and gain errors to at least the 14-bit
level. By performing a system offset CAL first and a system gain
calibration second, priority is given to reducing the gain error to
zero before reducing the offset error to zero. If the system errors
are small, a system offset calibration would be performed, fol-
lowed by a system gain calibration. If the systems errors are
large (close to the specified limits of the calibration range), this
cycle would be repeated twice to ensure that the offset and gain
errors were reduced to at least the 14-bit level. The advantage of
doing separate system offset and system gain calibrations is that
the user has more control over when the analog inputs need to
be at the required levels, and the CONVST signal does not have
to be used.
Alternatively, a system (gain + offset) calibration can be
performed. It is recommended to perform three system (gain +
offset) calibrations to reduce the offset and gain errors to the 14-
bit level. For the system (gain + offset) calibration priority is
given to reducing the offset error to zero before reducing the
gain error to zero. Thus if the system errors are small then two
system (gain + offset) calibrations will be sufficient. If the sys-
tem errors are large (close to the specified limits of the calibra-
tion range) three system (gain + offset) calibrations may be
AD7856
–23–REV. A
required to reduced the offset and gain errors to at least the 14-
bit level. There will never be any need to perform more than
three system (offset + gain) calibrations.
The zero scale error is adjusted for an offset calibration and the
positive full-scale error is adjusted for a gain calibration.
System Calibration Timing
The calibration timing diagram in Figure 29 is for a full system
calibration where the falling edge of CAL initiates an internal
reset before starting a calibration (note that if the part is in power-
down mode, the CAL pulsewidth must take account of the power-up
time). For software calibrations with power-down modes, see
note in Power-Up Times section. If a full system calibration is
to be performed in software it is easier to perform separate gain
and offset calibrations so that the CONVST bit in the control
register does not have to be programmed in the middle of the
system calibration sequence. The rising edge of CAL starts
calibration of the internal DAC and causes the BUSY line to go
high. If the control register is set for a full system calibration,
the CONVST must be used also. The full-scale system voltage
should be applied to the analog input pins from the start of
calibration. The BUSY line will go low once the DAC and Sys-
tem Gain Calibration are complete. Next the system offset volt-
age is applied to the AIN pin for a minimum setup time (t
SETUP
)
of 100 ns before the rising edge of the CONVST and remains
until the BUSY signal goes low. The rising edge of the CONVST
starts the system offset calibration section of the full system
calibration and also causes the BUSY signal to go high. The
BUSY signal will go low after a time t
CAL2
when the calibration
sequence is complete. In some applications not all the input
channels may be used. In this case it may be useful to dedicate
two input channels for the system calibration, one which has the
system offset voltage applied to it, and one which has the system
full scale voltage applied to it. When a system offset or gain
calibration is performed, the channel selected should correspond
to the system offset or system full-scale voltage channel.
The timing for a system (gain + offset) calibration is very similar
to that of Figure 29 the only difference being that the time t
CAL1
will be replaced by a shorter time of the order of t
CAL2
as the
internal DAC will not be calibrated. The BUSY signal will
signify when the gain calibration is finished and when the part is
ready for the offset calibration.
CONVST (I/P)
AIN (I/P)
t
16
t
SETUP
CAL (I/P)
BUSY (O/P)
t
1
t
15
t
1
= 100ns MIN,
t
16
= 2.5
t
CLKIN
MAX,
t
15
= 2.5
t
CLKIN
MAX,
t
CAL1
= 222228
t
CLKIN
MAX,
t
CAL2
= 27798
t
CLKIN
t
CAL1
t
CAL2
V
SYSTEM FULL SCALE
V
OFFSET
Figure 29. Timing Diagram for Full System Calibration
The timing diagram for a system offset or system gain calibra-
tion is shown in Figure 30. Here again the CAL is pulsed and
the rising edge of the CAL initiates the calibration sequence (or
the calibration can be initiated in software by writing to the
control register). The rising edge of the CAL causes the BUSY
line to go high and it will stay high until the calibration sequence is
finished. The analog input should be set at the correct level for a
minimum setup time (t
SETUP
) of 100 ns before the rising edge of
CAL and stay at the correct level until the BUSY signal goes low.
AIN (I/P)
t
SETUP
BUSY (O/P)
t
15
t
1
V
SYSTEM FULL SCALE
OR V
SYSTEM OFFSET
CAL (I/P)
t
CAL2
Figure 30. Timing Diagram for System Gain or System
Offset Calibration
SERIAL INTERFACE SUMMARY
Table IX details the two interface modes and the serial clock
edges from which the data is clocked out by the AD7856
(DOUT Edge) and that the data is latched in on (DIN Edge).
In both interface Modes 1, and 2 the SYNC is gated with the
SCLK. Thus the falling edge of SYNC may clock out the MSB
of data. Subsequent bits will be clocked out by the Serial Clock,
SCLK. The condition for the falling edge of SYNC clocking out
the MSB of data is as follows:
The falling edge of SYNC will clock out the MSB if the serial clock
is low when the SYNC goes low.
If this condition is not the case, the SCLK will clock out the
MSB. If a noncontinuous SCLK is used, it should idle high.
Table IX. SCLK Active Edges
Interface Mode DOUT Edge DIN Edge
1, 2 SCLK SCLK
Resetting the Serial Interface
When writing to the part via the DIN line there is the possibility
of writing data into the incorrect registers, such as the test regis-
ter for instance, or writing the incorrect data and corrupting the
serial interface. The SYNC pin acts as a reset. Bringing the
SYNC pin high resets the internal shift register. The first data
bit after the next SYNC falling edge will now be the first bit of a
new 16-bit transfer. It is also possible that the test register con-
tents were altered when the interface was lost. Therefore, once
the serial interface is reset it may be necessary to write the 16-bit
word 0100 0000 0000 0010 to restore the test register to its
default value. Now the part and serial interface are completely
reset. It is always useful to retain the ability to program the
SYNC line from a port of the µController/DSP to have the abil-
ity to reset the serial interface.
Table X summarizes the interface modes provided by the
AD7856. It also outlines the various µP/µC to which the par-
ticular interface is suited.
Interface Mode 1 may only be set by programming the control
register (See section on Control Register).
Some of the more popular µProcessors, µControllers, and DSP
machines that the AD7856 will interface to directly are men-
tioned here. This does not cover all µCs, µPs and DSPs. A more
detailed timing description on each of the interface modes follows.

AD7856AR

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 5V SGL-Supply 8-Ch 14B 285kSPS
Lifecycle:
New from this manufacturer.
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