ADM6305/ADM6306 Data Sheet
Rev. B | Page 8 of 12
THEORY OF OPERATION
The ADM6305/ADM6306 are compact, low power supervisory
circuits capable of monitoring two voltage rails. If a monitored
voltage drops below its associated threshold, the active low reset
output asserts low.
The ADM6305 monitors two supplies via two adjustable
resistor-programmable undervoltage reset inputs. Both RST
IN1 and RST IN2 have a reset threshold of either 0.4 V or
1.23 V depending on the particular model; that is, the RST
IN1 and RST IN2 threshold of the ADM6305DxARJZ model
is 1.23 V, while in the case of ADM6305DxARJZ1 model, it is
0.4 V. The V
CC
input of the ADM6305 is not a monitored input.
The ADM6306 has one adjustable undervoltage reset input,
RST IN, which features a choice of reset threshold, 0.4 V or
1.23 V (see the Ordering Guide for more information). The
ADM6306 incorporates a variety of internally pretrimmed V
CC
undervoltage threshold options for monitoring supply voltages
in increments between 2.5 V to 5 V. The ADM6306 also
includes a manual reset input.
INPUT CONFIGURATION
The threshold voltage at an adjustable input is either 0.4 V or
1.23 V. To monitor a voltage greater than the typical adjustable
threshold, V
RSTH
, connect a resistor divider network to the
circuit as depicted in Figure 14, where
R2
R2R1
VV
RSTHTH
Figure 14. Setting the Adjustable Monitor
The high input impedance (leakage of ±25 nA) of the adjustable
inputs minimizes the offset error caused by the leakage current
and external resistor divider. This allows the user to apply a divider
with large resistance to minimize the loss. The offset voltage
caused by the leakage current is calculated by R1 × ±25 nA.
The RST INx inputs are designed to ignore fast voltage
transients (see Figure 11 and Figure 12). Increase the noise
immunity by connecting a 0.1 µF bypass capacitor between
RST INx and ground. Note that adding capacitance to RST
INx slows the overall response time of the device.
There is no hysteresis associated with the 0.4 V adjustable
inputs; instead, a time-based glitch filter to prevent false
triggering is used. The glitch filter avoids the need to use a
portion of the operating supply range to provide hysteresis
on this input. The ADM6305/ADM6306 are powered via V
CC
.
Figure 9 shows the maximum transient duration vs. V
CC
reset
threshold overdrive, for which reset pulses are not generated.
Figure 9 depicts the maximum pulse width that a negative going
V
CC
transient may typically have without causing
RESET
to be
asserted. As the amplitude of the transient increases, the
maximum allowable pulse width decreases. The addition of a
bypass capacitor on V
CC
provides additional transient immunity.
RESET OUTPUT CONFIGURATION
The ADM6305/ADM6306 are available in a choice of four
reset timeouts. Once the monitored supplies rise above their
associated threshold level, the
RESET
signal remains low for
the reset timeout period before deasserting. Subsequently, if
a monitored supply falls below its associated threshold, the
RESET
output reasserts. The open-drain
RESET
output of the
ADM6305/ADM6306 remains valid as long as V
CC
exceeds 0.9 V.
The ADM6305 remains in UVLO when V
CC
is below 1.5 V. The
RESET
output is controlled by RTS INx if V
CC
exceeds 2.5 V.
The open-drain
RESET
output allows the ADM6305 and
ADM6306 to interface easily with microprocessors and
devices with bidirectional reset pins. Connecting the supervi-
sory devices
RESET
output directly to the microcontrollers
RESET
pin with a single pull-up resistor allows either device
to issue a system reset (see Figure 15).
Figure 15. Interfacing to Microprocessors with Bidirectional
RESET
Output
MANUAL RESET
The ADM6306 features a manual reset input (
MR
) which, when
driven low, asserts the reset output. When
MR
transitions from
low to high, reset remains asserted for the duration of the reset
active timeout period before deasserting. The
MR
input has a
63.5 k internal pull-up resistor so that the input is always
high when unconnected. An external push-button switch can
be connected between
MR
and ground so that the user can
generate a reset. Debounce circuitry is integrated on-chip for
this purpose. Noise immunity is provided on the
MR
input,
and fast, negative-going transients of up to 0.1 µs (typical) are
ignored. If required, a 0.1 F capacitor between
MR
and ground
provides additional noise immunity.
R2
R1
V
RSTH
IN
09345-014
ADM6305/
ADM6306
RESET
V
CC
MICROPROCESSOR
RESET
R
PULL-UP
09345-015
