ADM691A/ADM693A/ADM800L/M
–10–
REV. 0
APPLICATIONS INFORMATION
INCREASING THE DRIVE CURRENT
If the continuous output current requirements at V
OUT
exceeds
250 mA or if a lower V
CC
–V
OUT
voltage differential is desired, an
external PNP pass transistor may be connected in parallel with
the internal transistor. The BATT ON output can drive the
base of the external transistor via a current limiting transistor.
0.1µF
+5V
INPUT
POWER
V
CC
BATT
ON
V
BATT
BATTERY
PNP
TRANSISTOR
V
OUT
0.1µF
Figure 21. Increasing the Drive Current
Using a Rechargeable Battery for Backup
If a capacitor or a rechargeable battery is used for backup, then
the charging resistor should be connected to V
OUT
since this
eliminates the discharge path that would exist during power
down if the resistor were connected to V
CC.
RECHARGEABLE
BATTERY
V
OUT
– V
BATT
R
I =
R
ADM69_A
ADM800_
0.1µF
+5V
INPUT
POWER
V
CC
V
BATT
V
OUT
0.1µF
Figure 22. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is noninverting,
hysteresis can be added simply by connecting a resistor between
the
PFO output and the PFI input as shown in Figure 23. When
PFO is low, resistor R3 sinks current from the summing junction
at the PFI pin. When
PFO is high, R3 sources current into the
PFI summing junction. This results in differing trip levels for the
comparator. Resistors R1 and R2 therefore set the trip point
while R3 adds hysteresis. R3 should be larger than 10 kΩ so that
it does not cause excessive loading on the PFO output. Addi-
tional noise rejection and filtering may be achieved by adding a
capacitor from PFI to GND.
1.25V
(PFO)
INPUT
POWER
R1
R2
PFI
R3
TO
µP NMI
5V
PFO
0V
0V V
L
V
M
V
IN
V
H
=
1.25
1
+ R
1
R
2
+R
3
R
2
×
R
3
V
L
= 1
.25
+R
1
1.25
V
CC
–
1.25
R
2
R
3
V
MID
=
1.25
R
1
+R
2
R
2
Figure 23. Adding Hysteresis to the Power Fail Comparator
Typical Operating Circuit
A typical operating circuit is shown in Figure 24. The circuit
features power supply monitoring, battery backup switching
and watchdog timing.
CMOS RAM is powered from V
OUT
. When 5 V power is
present, this is routed to V
OUT
. If V
CC
fails, then V
BATT
is
routed to V
OUT
. V
OUT
can supply up to 250 mA from V
CC
, but
if more current is required, an external PNP transistor can be
added. When V
CC
is higher than V
BATT
and the reset threshold,
BATT ON goes low, providing base drive for the external tran-
sistor. When V
CC
is lower than V
BATT
and the reset threshold,
an internal 7 Ω. MOSFET connects the backup battery to
V
OUT
.
Reset Output
The internal voltage detector monitors V
CC
and generates a
RESET output to hold the microprocessor’s RESET line low
when V
CC
is below the reset threshold. An internal timer holds
RESET low for 200 ms after V
CC
rises above the threshold.
This prevents repeated toggling of
RESET even if the 5 V
power drops out and recovers with each power line cycle.
Early Power Fail Detector
The input power line is monitored via a resistive potential di-
vider connected to the Power Fail Input (PFI). When the volt-
age at PFI falls below 1.25 V, the Power Fail Output (
PFO)
drives the processor’s NMI input low. If a Power Fail threshold
of 7 V is set with resistors R1 and R2, the microprocessor will
have the time when V
CC
drops below 7 V to save data into
RAM. Power supply capacitance will extend the time available.
This will allow more time for microprocessor housekeeping
tasks to be completed before power is lost.
