ATA CF
AP-CFxxxxH4NR-XXXXXXQ
7
© 2013 Apacer Technology Inc. Rev. 1.6
5. Flash Management
5.1. Advanced wear-leveling algorithms
Flash memory devices differ from Hard Disk Drives (HDDs) in terms of how blocks are utilized. For HDDs,
when a change is made to stored data, like erase or update, the controller mechanism on HDDs will
perform overwrites on blocks. Unlike HDDs, flash blocks cannot be overwritten and each P/E cycle wears
down the lifespan of blocks gradually. Repeatedly program/erase cycles performed on the same memory
cells will eventually cause some blocks to age faster than others. This would bring flash storages to their
end of service term sooner. Wear leveling is an important mechanism that level out the wearing of blocks
so that the wearing-down of blocks can be almost evenly distributed. This will increase the lifespan of
SSDs. Commonly used wear leveling types are Static and Dynamic.
5.2 S.M.A.R.T. technology
S.M.A.R.T. is an acronym for Self-Monitoring, Analysis and Reporting Technology, an open standard
allowing disk drives to automatically monitor their own health and report potential problems. It protects the
user from unscheduled downtime by monitoring and storing critical drive performance and calibration
parameters. Ideally, this should allow taking proactive actions to prevent impending drive failure. Apacer
SMART feature adopts the standard SMART command B0h to read data from the drive. When the Apacer
SMART Utility running on the host, it analyzes and reports the disk status to the host before the device is
in critical condition.
5.3 Built-in hardware ECC
The ATA-Disk Module uses BCH Error Detection Code (EDC) and Error Correction Code (ECC)
algorithms which correct up to eight random single-bit errors for each 512-byte block of data. High
performance is fulfilled through hardware-based error detection and correction.
5.4 Flash block management
Current production technology is unable to guarantee total reliability of NAND flash memory array. When
a flash memory device leaves factory, it comes with a minimal number of initial bad blocks during
production or out-of-factory as there is no currently known technology that produce flash chips free of bad
blocks. In addition, bad blocks may develop during program/erase cycles. When host performs
program/erase command on a block, bad block may appear in Status Register. Since bad blocks are
inevitable, the solution is to keep them in control. Apacer flash devices are programmed with ECC, block
mapping technique and S.M.A.R.T to reduce invalidity or error. Once bad blocks are detected, data in
those blocks will be transferred to free blocks and error will be corrected by designated algorithms.
5.5 Power Failure Management
Power Failure Management plays a crucial role when experiencing unstable power supply. Power
disruption may occur when users are storing data into the SSD. In this urgent situation, the controller
would run multiple write-to-flash cycles to store the metadata for later block rebuilding. This urgent
operation requires about several milliseconds to get it done. At the next power up, the firmware will
perform a status tracking to retrieve the mapping table and resume previously programmed NAND blocks
to check if there is any incompleteness of transmission.
