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ADT7311WTRZ-RL7

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ADT7311 Data Sheet
Rev. 0 | Page 18 of 24
WRITING DATA
Data is written to the ADT7311 in eight bits or 16 bits, depending
on the addressed register. The first byte written to the device is
the command byte, with the read/write bit set to 0. The master
then supplies the 8-bit or 16-bit input data on the DIN line.
The ADT7311 clocks the data into the register addressed in
the command byte on the positive edge of SCLK. The master
finishes the write by pulling
CS
high.
Figure 15 shows a write to an 8-bit register, and Figure 16 shows
a write to a 16-bit register.
The master must begin a new write transaction on the bus for
every register write. Only one register is written to per bus
transaction.
C3
C2
C5
C4
DIN
C7
C6
C1
D2 D1 D0
C0
8-BIT DATA
5 6 7 8 9 10111213141516
SCLK
1234
D5
CS
R/W REGISTER ADDR
0
000
D4 D3D7 D6
8-BIT COMMAND BYTE
09050-028
Figure 15. Writing to an 8-Bit Register
C3 C2C5 C4
DIN
C7 C6 C1 D2 D1 D0
C0
16-BIT DATA
5
24
6 7 8 9 10 11 12 13 14 15 16
22 23
SCLK
1234
D14 D13
17
CS
R/W REGISTER ADDR
0
00
0
D12 D10D11 D9 D8 D7D15
8-BIT COMMAND BYTE
09050-029
Figure 16. Writing to a 16-Bit Register
Data Sheet ADT7311
Rev. 0 | Page 19 of 24
READING DATA
A read transaction begins when the master writes the command
byte to the ADT7311 with the read/write bit set to 1. The master
then supplies eight or 16 clock pulses, depending on the addressed
register, and the ADT7311 clocks out data from the addressed
register on the DOUT line. Data is clocked out on the first
falling edge of SCLK following the command byte.
The read transaction finishes when the master takes
CS
high.
INTERFACING TO DSPs OR MICROCONTROLLERS
The ADT7311 can be operated with
CS
used as a frame syn-
chronization signal. This scheme is useful for DSP interfaces.
In this case, the first bit (MSB) is effectively clocked out by
CS
because
CS
normally occurs after the falling edge of SCLK in
DSPs. SCLK can continue to run between data transfers,
provided that the timing specifications in Table 2 are obeyed.
CS
can be tied to ground, and the serial interface can be
operated in a 3-wire mode. DIN, DOUT, and SCLK are
used to communicate with the ADT7311 in this mode.
For microcontroller interfaces, it is recommended that SCLK
idle high between data transfers.
SERIAL INTERFACE RESET
The serial interface can be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the ADT7311 line for at
least 32 serial clock cycles, the serial interface is reset. This
ensures that the interface can be reset to a known state if the
interface gets lost due to a software error or some glitch in the
system. Reset returns the interface to the state in which it is
expecting a write to the communications register. This opera-
tion resets the contents of all registers to their power-on values.
Following a reset, the user should allow a period of 500 μs
before addressing the serial interface.
09050-030
C3
C2
C5
C4
DIN
C7 C6
C1
C0
8-BIT DATA
5
6
78
9
10
11 12
13 14 15
16
SCLK
1
23
4
D6 D5
CS
R/W REGISTER ADDR
0
0
0
D4
D3 D2 D1 D0
D7
DOUT
8-BIT COMMAND WORD
0
Figure 17. Reading from an 8-Bit Register
0
9050-031
C3
C2
C5
C4
DIN
C7
C6
C1
D2
D1
D0
C0
16-BIT DATA
5
24
6 7 8 9 10 11 12 13 14 15 16
22
23
SCLK
1234
D14
D13
17
CS
R/W REGISTER ADDR
0
0
0
D12
D11
D10
D9
D8 D7
D15
DOUT
8-BIT COMMAND BYTE
0
Figure 18. Reading from a 16-Bit Register
ADT7311 Data Sheet
Rev. 0 | Page 20 of 24
INT AND CT OUTPUTS
The INT and CT pins are open-drain outputs, and both pins
require a 10 kΩ pull-up resistor to V
DD
. The ADT7311 must be
fully powered up to V
DD
before reading INT and CT data.
UNDERTEMPERATURE AND OVERTEMPERATURE
DETECTION
The INT and CT pins have two undertemperature/over-
temperature modes: comparator mode and interrupt mode.
The interrupt mode is the default power-up overtemperature
mode. The INT output pin becomes active when the tempera-
ture is greater than the temperature stored in the T
HIGH
setpoint
register or less than the temperature stored in the T
LOW
setpoint
register. How this pin reacts after this event depends on the
overtemperature mode selected.
Figure 19 illustrates the comparator and interrupt modes for
events exceeding the T
HIGH
limit with both pin polarity settings.
Figure 20 illustrates the comparator and interrupt modes for
events exceeding the T
LOW
limit with both pin polarity settings.
Comparator Mode
In comparator mode, the INT pin returns to its inactive status
when the temperature drops below the T
HIGH
− T
HYST
limit or
rises above the T
LOW
+ T
HYST
limit.
Putting the ADT7311 into shutdown mode does not reset the
INT state in comparator mode.
Interrupt Mode
In interrupt mode, the INT pin goes inactive when any ADT7311
register is read. When the INT pin is reset, it goes active again
only when the temperature is greater than the temperature
stored in the T
HIGH
setpoint register or less than the temperature
stored in the T
LOW
setpoint register.
Placing the ADT7311 into shutdown mode resets the INT pin
in the interrupt mode.
TEMPE
R
A
TURE
82°C
81°C
80°C
79°C
78°C
77°C
76°C
75°C
74°C
73°C
INT PIN
(COMPARATOR MODE)
POLARITY = ACTIVE LOW
INT PIN
(INTERRUPT MODE)
POLARITY = ACTIVE LOW
INT PIN
(INTERRUPT MODE)
POLARITY = ACTIVE HIGH
INT PIN
(COMPARATOR MODE)
POLARITY = ACTIVE HIGH
T
HIGH
T
HIGH
– T
HYST
TIME
READ
READ READ
09050-020
Figure 19. INT Output Temperature Response Diagram for T
HIGH
Overtemperature Events
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ADT7311WTRZ-RL7

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Buy ADT7311WTRZ-RL7
Manufacturer:
Analog Devices Inc.
Description:
SENSOR DIGITAL -40C-150C 8SOIC
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