Detailed Description
The MAX4699/MAX4701 are low-voltage CMOS analog
switches that operate from a single +1.8V to +5.5V
power supply. The MAX4702 requires an additional
logic supply that allows for setting lower logic thresh-
olds. The MAX4699/MAX4701 are double-pole/double-
throw (DPDT) devices. The MAX4702 is a quad
single-pole/double-throw (SPDT) device. These devices
feature a break-before-make switching, fast switching
speeds (with V+ = 5V: t
ON
= 18ns max, t
OFF
= 9ns max
and with V+ = 3V: t
ON
= 35ns, t
OFF
= 20) and rail-to-rail
signal handling. A logic input on the MAX4702 allows
for logic thresholds as low as 1.0V.
Applications Information
Analog Signal Levels
Analog signals that range over the entire supply voltage
(V+ to GND) can be passed with very little change in on-
resistance (see
Typical Operating Characteristics
). The
switches are bidirectional, so the NO, NC, and COM pins
can be used as either inputs or outputs.
_______________________________________________________________________________________ 7
MAX4699/MAX4701/MAX4702
Low-Voltage, Dual DPDT/Quad SPDT
Analog Switches in QFN
Pin Description
TQFN-EP PIN TSSOP PIN
MAX4699/
MAX4701
MAX4702 MAX4701 MAX4702
NAME FUNCTION
1 1 3 3 NC1 Analog Switch 1—Normally Closed Terminal
2 4 IN Digital Control Input Switch 1, 2, 3, and 4
2 4 IN1, IN2 Digital Control Input Switch 1 and 2
3 3 5 5 NO2 Analog Switch 2—Normally Open Terminal
4 4 6 6 COM2 Analog Switch 2—Common Terminal
5 5 7 7 NC2 Analog Switch 2—Normally Closed Terminal
6 6 8 8 GND Ground
7 7 9 9 NO3 Analog Switch 3—Normally Open Terminal
8 8 10 10 COM3 Analog Switch 3—Common Terminal
9 9 11 11 NC3 Analog Switch 3—Normally Closed Terminal
— 10 — 12 V
L
Logic Power-Supply Input
10 12 IN3, IN4 Digital Control Input Switch 3 and 4
11 11 13 13 NO4 Analog Switch 4—Normally Open Terminal
12 12 14 14 COM4 Analog Switch 4—Common Terminal
13 13 15 15 NC4 Analog Switch 4—Normally Closed Terminal
14 14 16 16 V+ Positive Supply Voltage Input
15 15 1 1 NO1 Analog Switch 1—Normally Open Terminal
16 16 2 2 COM1 Analog Switch 1—Common Terminal
EP Exposed Pad (TQFN Only). Connect EP to GND.
POSITIVE SUPPLY
COM
NO
D2
D1
GND
V
g
V+
MAX4699
MAX4701
MAX4702
Figure 1. Overvoltage Protection Using Two External Blocking
Diodes
MAX4699/MAX4701/MAX4702
Power-Supply Sequencing and
Overvoltage Protection
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
may cause permanent damage to the devices.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply V+ before applying
analog signals, especially if the analog signal is not cur-
rent limited. If this sequencing is not possible, and if the
analog inputs are not current limited to <20mA, add a
small-signal diode (D1) as shown in Figure 1. If the ana-
log signal can dip below GND, add D2. Adding protec-
tion diodes reduces the analog range to a diode drop
(about 0.7V) below V+ (for D1), and a diode drop above
ground (for D2). On-resistance increases slightly at low
supply voltages. Maximum supply voltage (V+) must not
exceed +6V.
Adding protection diode D2 causes the logic threshold
to be shifted relative to GND. TTL compatibility is not
guaranteed when D2 is added.
Protection diodes D1 and D2 also protect against some
overvoltage situations. With Figure 1’s circuit, if the sup-
ply voltage is below the absolute maximum rating, and
if a fault voltage up to the absolute maximum rating is
applied to an analog signal pin, no damage will result.
V
L
Logic Input (MAX4702)
The MAX4702 features a V
L
logic input that allows for
lower logic input thresholds down to 1.0V min for V
IH
in
the quad SPDT configuration. Power-up V
L
after V+ has
been powered with a minimum of 1.5V to ensure proper
operation of the device.
Low-Voltage, Dual DPDT/Quad SPDT
Analog Switches in QFN
8 _______________________________________________________________________________________
t
r
< 5ns
t
f
< 5ns
50%
V
IL
LOGIC
INPUT
R
L
300Ω
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
N_ (
R
L
)
R
L
+ R
ON
V
N_
V
IH
t
OFF
0
NO_
OR NC_
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
C
L
35pF
V+
V
OUT
MAX4699
MAX4701
MAX4702
Figure 2. Switching Time
50%
V
IH
V
IL
LOGIC
INPUT
V
OUT
0.9 x V
OUT
t
D
LOGIC
INPUT
R
L
300Ω
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
V
OUT
V+
V+
C
L
35pF
V
N_
COM_
MAX4699
MAX4701
MAX4702
Figure 3. Break-Before-Make Interval
Test Circuits/Timing Diagrams
MAX4699/MAX4701/MAX4702
Low-Voltage, Dual DPDT/Quad SPDT
Analog Switches in QFN
_______________________________________________________________________________________ 9
V
GEN
GND
COM_
C
L
V
OUT
V+
V
OUT
IN_
OFF
ON
OFF
ΔV
OUT
Q = (ΔV
OUT
)(C
L
)
NC_
OR NO_
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN_
V
IL
TO V
IH
V+
R
GEN
IN
MAX4699
MAX4701
MAX4702
Figure 4. Charge Injection
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO ALL OTHER CHANNELS.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
V+
V
OUT
V+
IN_
NC_
COM_
NO_
V
IN
MAX4699
MAX4701
MAX4702
OFF-ISOLATION = 20log
V
OUT
V
IN
ON-LOSS = 20log
V
OUT
V
IN
CROSSTALK = 20log
V
OUT
V
IN
NETWORK
ANALYZER
50Ω
50Ω 50Ω
50Ω
MEAS REF
10nF
V OR V+
50Ω
GND
Figure 5. On-Loss, Off-Isolation, and Crosstalk
CAPACITANCE
METER
NC_ or
NO_
COM_
GND
IN_
V
IL
OR
V
IH
10nF
V+
f = 1MHz
V+
MAX4699
MAX4701
MAX4702
Figure 6. Channel Off/On-Capacitance
Test Circuits/Timing Diagrams (continued)
Chip Information
SUBSTRATE CONNECTED TO GND

MAX4701ETE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog Switch ICs 2Ch DPDT Analog Switch
Lifecycle:
New from this manufacturer.
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